1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2011 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <i2c.h>
9*4882a593Smuzhiyun #include <hwconfig.h>
10*4882a593Smuzhiyun #include <asm/mmu.h>
11*4882a593Smuzhiyun #include <fsl_ddr_sdram.h>
12*4882a593Smuzhiyun #include <fsl_ddr_dimm_params.h>
13*4882a593Smuzhiyun #include <asm/fsl_law.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun struct board_specific_parameters {
18*4882a593Smuzhiyun u32 n_ranks;
19*4882a593Smuzhiyun u32 datarate_mhz_high;
20*4882a593Smuzhiyun u32 clk_adjust;
21*4882a593Smuzhiyun u32 wrlvl_start;
22*4882a593Smuzhiyun u32 cpo;
23*4882a593Smuzhiyun u32 write_data_delay;
24*4882a593Smuzhiyun u32 force_2t;
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /*
28*4882a593Smuzhiyun * This table contains all valid speeds we want to override with board
29*4882a593Smuzhiyun * specific parameters. datarate_mhz_high values need to be in ascending order
30*4882a593Smuzhiyun * for each n_ranks group.
31*4882a593Smuzhiyun *
32*4882a593Smuzhiyun * ranges for parameters:
33*4882a593Smuzhiyun * wr_data_delay = 0-6
34*4882a593Smuzhiyun * clk adjust = 0-8
35*4882a593Smuzhiyun * cpo 2-0x1E (30)
36*4882a593Smuzhiyun */
37*4882a593Smuzhiyun static const struct board_specific_parameters dimm0[] = {
38*4882a593Smuzhiyun /*
39*4882a593Smuzhiyun * memory controller 0
40*4882a593Smuzhiyun * num| hi| clk| wrlvl | cpo |wrdata|2T
41*4882a593Smuzhiyun * ranks| mhz|adjst| start | delay|
42*4882a593Smuzhiyun */
43*4882a593Smuzhiyun {2, 750, 3, 5, 0xff, 2, 0},
44*4882a593Smuzhiyun {2, 1250, 4, 6, 0xff, 2, 0},
45*4882a593Smuzhiyun {2, 1350, 5, 7, 0xff, 2, 0},
46*4882a593Smuzhiyun {2, 1666, 5, 8, 0xff, 2, 0},
47*4882a593Smuzhiyun {}
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)50*4882a593Smuzhiyun void fsl_ddr_board_options(memctl_options_t *popts,
51*4882a593Smuzhiyun dimm_params_t *pdimm,
52*4882a593Smuzhiyun unsigned int ctrl_num)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
55*4882a593Smuzhiyun ulong ddr_freq;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun if (ctrl_num) {
58*4882a593Smuzhiyun printf("Wrong parameter for controller number %d", ctrl_num);
59*4882a593Smuzhiyun return;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun if (!pdimm->n_ranks)
62*4882a593Smuzhiyun return;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun pbsp = dimm0;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /*
67*4882a593Smuzhiyun * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
68*4882a593Smuzhiyun * freqency and n_banks specified in board_specific_parameters table.
69*4882a593Smuzhiyun */
70*4882a593Smuzhiyun ddr_freq = get_ddr_freq(0) / 1000000;
71*4882a593Smuzhiyun while (pbsp->datarate_mhz_high) {
72*4882a593Smuzhiyun if (pbsp->n_ranks == pdimm->n_ranks) {
73*4882a593Smuzhiyun if (ddr_freq <= pbsp->datarate_mhz_high) {
74*4882a593Smuzhiyun popts->cpo_override = pbsp->cpo;
75*4882a593Smuzhiyun popts->write_data_delay =
76*4882a593Smuzhiyun pbsp->write_data_delay;
77*4882a593Smuzhiyun popts->clk_adjust = pbsp->clk_adjust;
78*4882a593Smuzhiyun popts->wrlvl_start = pbsp->wrlvl_start;
79*4882a593Smuzhiyun popts->twot_en = pbsp->force_2t;
80*4882a593Smuzhiyun goto found;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun pbsp_highest = pbsp;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun pbsp++;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun if (pbsp_highest) {
88*4882a593Smuzhiyun printf("Error: board specific timing not found "
89*4882a593Smuzhiyun "for data rate %lu MT/s!\n"
90*4882a593Smuzhiyun "Trying to use the highest speed (%u) parameters\n",
91*4882a593Smuzhiyun ddr_freq, pbsp_highest->datarate_mhz_high);
92*4882a593Smuzhiyun popts->cpo_override = pbsp_highest->cpo;
93*4882a593Smuzhiyun popts->write_data_delay = pbsp_highest->write_data_delay;
94*4882a593Smuzhiyun popts->clk_adjust = pbsp_highest->clk_adjust;
95*4882a593Smuzhiyun popts->wrlvl_start = pbsp_highest->wrlvl_start;
96*4882a593Smuzhiyun popts->twot_en = pbsp_highest->force_2t;
97*4882a593Smuzhiyun } else {
98*4882a593Smuzhiyun panic("DIMM is not supported by this board");
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun found:
102*4882a593Smuzhiyun /*
103*4882a593Smuzhiyun * Factors to consider for half-strength driver enable:
104*4882a593Smuzhiyun * - number of DIMMs installed
105*4882a593Smuzhiyun */
106*4882a593Smuzhiyun popts->half_strength_driver_enable = 0;
107*4882a593Smuzhiyun /* Write leveling override */
108*4882a593Smuzhiyun popts->wrlvl_override = 1;
109*4882a593Smuzhiyun popts->wrlvl_sample = 0xf;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /* Rtt and Rtt_WR override */
112*4882a593Smuzhiyun popts->rtt_override = 0;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /* Enable ZQ calibration */
115*4882a593Smuzhiyun popts->zq_en = 1;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun /* DHC_EN =1, ODT = 60 Ohm */
118*4882a593Smuzhiyun popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
dram_init(void)121*4882a593Smuzhiyun int dram_init(void)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun phys_size_t dram_size = 0;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun puts("Initializing....");
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun if (fsl_use_spd()) {
128*4882a593Smuzhiyun puts("using SPD\n");
129*4882a593Smuzhiyun dram_size = fsl_ddr_sdram();
130*4882a593Smuzhiyun } else {
131*4882a593Smuzhiyun puts("no SPD and fixed parameters\n");
132*4882a593Smuzhiyun return -ENXIO;
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun dram_size = setup_ddr_tlbs(dram_size / 0x100000);
136*4882a593Smuzhiyun dram_size *= 0x100000;
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun debug(" DDR: ");
139*4882a593Smuzhiyun gd->ram_size = dram_size;
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun return 0;
142*4882a593Smuzhiyun }
143