1*4882a593Smuzhiyun /** 2*4882a593Smuzhiyun * Copyright 2011 Freescale Semiconductor 3*4882a593Smuzhiyun * Author: Mingkai Hu <Mingkai.hu@freescale.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This file provides support for the ngPIXIS, a board-specific FPGA used on 8*4882a593Smuzhiyun * some Freescale reference boards. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * CPLD register set. Feel free to add board-specific #ifdefs where necessary. 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun typedef struct cpld_data { 15*4882a593Smuzhiyun u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */ 16*4882a593Smuzhiyun u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */ 17*4882a593Smuzhiyun u8 pcba_ver; /* 0x2 - PCBA Revision Register */ 18*4882a593Smuzhiyun u8 system_rst; /* 0x3 - system reset register */ 19*4882a593Smuzhiyun u8 res0; /* 0x4 - not used */ 20*4882a593Smuzhiyun u8 sw_ctl_on; /* 0x5 - Switch Control Enable Register */ 21*4882a593Smuzhiyun u8 por_cfg; /* 0x6 - POR Control Register */ 22*4882a593Smuzhiyun u8 switch_strobe; /* 0x7 - Multiplexed pin Select Register */ 23*4882a593Smuzhiyun u8 jtag_sel; /* 0x8 - JTAG or AURORA Selection */ 24*4882a593Smuzhiyun u8 sdbank1_clk; /* 0x9 - SerDes Bank1 Reference clock */ 25*4882a593Smuzhiyun u8 sdbank2_clk; /* 0xa - SerDes Bank2 Reference clock */ 26*4882a593Smuzhiyun u8 fbank_sel; /* 0xb - Flash bank selection */ 27*4882a593Smuzhiyun u8 serdes_mux; /* 0xc - Multiplexed pin Select Register */ 28*4882a593Smuzhiyun u8 sw[1]; /* 0xd - SW2 Status */ 29*4882a593Smuzhiyun u8 system_rst_default; /* 0xe - system reset to default register */ 30*4882a593Smuzhiyun u8 sysclk_sw1; /* 0xf - sysclk configuration register */ 31*4882a593Smuzhiyun } __attribute__ ((packed)) cpld_data_t; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define SERDES_MUX_LANE_6_MASK 0x2 34*4882a593Smuzhiyun #define SERDES_MUX_LANE_6_SHIFT 1 35*4882a593Smuzhiyun #define SERDES_MUX_LANE_A_MASK 0x1 36*4882a593Smuzhiyun #define SERDES_MUX_LANE_A_SHIFT 0 37*4882a593Smuzhiyun #define SERDES_MUX_LANE_C_MASK 0x4 38*4882a593Smuzhiyun #define SERDES_MUX_LANE_C_SHIFT 2 39*4882a593Smuzhiyun #define SERDES_MUX_LANE_D_MASK 0x8 40*4882a593Smuzhiyun #define SERDES_MUX_LANE_D_SHIFT 3 41*4882a593Smuzhiyun #define CPLD_SWITCH_BANK_ENABLE 0x40 42*4882a593Smuzhiyun #define CPLD_SYSCLK_83 0x1 /* system clock 83.3MHz */ 43*4882a593Smuzhiyun #define CPLD_SYSCLK_100 0x2 /* system clock 100MHz */ 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* Pointer to the CPLD register set */ 46*4882a593Smuzhiyun #define cpld ((cpld_data_t *)CPLD_BASE) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* The CPLD SW register that corresponds to board switch X, where x >= 1 */ 49*4882a593Smuzhiyun #define CPLD_SW(x) (cpld->sw[(x) - 2]) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun u8 cpld_read(unsigned int reg); 52*4882a593Smuzhiyun void cpld_write(unsigned int reg, u8 value); 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define CPLD_READ(reg) cpld_read(offsetof(cpld_data_t, reg)) 55*4882a593Smuzhiyun #define CPLD_WRITE(reg, value) cpld_write(offsetof(cpld_data_t, reg), value) 56