1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2013 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <common.h> 8*4882a593Smuzhiyun #include <asm/mmu.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun struct fsl_e_tlb_entry tlb_table[] = { 11*4882a593Smuzhiyun /* TLB 0 - for temp stack in cache */ 12*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 13*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR_PHYS, 14*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 15*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 16*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , 17*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 18*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 19*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 20*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , 21*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 22*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 23*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 24*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , 25*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 26*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 27*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* TLB 1 */ 30*4882a593Smuzhiyun /* *I*** - Covers boot page */ 31*4882a593Smuzhiyun SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 32*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, 33*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 1), 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* *I*G* - CCSRBAR */ 36*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 37*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 38*4882a593Smuzhiyun 0, 1, BOOKE_PAGESZ_1M, 1), 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #ifndef CONFIG_SPL_BUILD 41*4882a593Smuzhiyun /* W**G* - Flash, localbus */ 42*4882a593Smuzhiyun /* This will be changed to *I*G* after relocation to RAM. */ 43*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 44*4882a593Smuzhiyun MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 45*4882a593Smuzhiyun 0, 2, BOOKE_PAGESZ_64M, 1), 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* W**G* - Flash, localbus */ 48*4882a593Smuzhiyun /* This will be changed to *I*G* after relocation to RAM. */ 49*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_SSD_BASE, CONFIG_SYS_SSD_BASE_PHYS, 50*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 51*4882a593Smuzhiyun 0, 5, BOOKE_PAGESZ_1M, 1), 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #ifdef CONFIG_PCI 54*4882a593Smuzhiyun /* *I*G* - PCI memory 1.5G */ 55*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 56*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 57*4882a593Smuzhiyun 0, 3, BOOKE_PAGESZ_1G, 1), 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* *I*G* - PCI I/O effective: 192K */ 60*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 61*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 62*4882a593Smuzhiyun 0, 4, BOOKE_PAGESZ_256K, 1), 63*4882a593Smuzhiyun #endif 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #endif 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #ifdef CONFIG_SYS_RAMBOOT 68*4882a593Smuzhiyun /* *I*G - eSDHC boot */ 69*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 70*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 71*4882a593Smuzhiyun 0, 8, BOOKE_PAGESZ_1G, 1), 72*4882a593Smuzhiyun #endif 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun int num_tlb_entries = ARRAY_SIZE(tlb_table); 77