1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2013 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/mmu.h>
9*4882a593Smuzhiyun #include <asm/immap_85xx.h>
10*4882a593Smuzhiyun #include <asm/processor.h>
11*4882a593Smuzhiyun #include <fsl_ddr_sdram.h>
12*4882a593Smuzhiyun #include <fsl_ddr_dimm_params.h>
13*4882a593Smuzhiyun #include <asm/io.h>
14*4882a593Smuzhiyun #include <asm/fsl_law.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun /* Fixed sdram init -- doesn't use serial presence detect. */
fixed_sdram(void)17*4882a593Smuzhiyun phys_size_t fixed_sdram(void)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun sys_info_t sysinfo;
20*4882a593Smuzhiyun char buf[32];
21*4882a593Smuzhiyun size_t ddr_size;
22*4882a593Smuzhiyun fsl_ddr_cfg_regs_t ddr_cfg_regs = {
23*4882a593Smuzhiyun .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
24*4882a593Smuzhiyun .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
25*4882a593Smuzhiyun .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
26*4882a593Smuzhiyun #if CONFIG_CHIP_SELECTS_PER_CTRL > 1
27*4882a593Smuzhiyun .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
28*4882a593Smuzhiyun .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
29*4882a593Smuzhiyun .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
30*4882a593Smuzhiyun #endif
31*4882a593Smuzhiyun .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
32*4882a593Smuzhiyun .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
33*4882a593Smuzhiyun .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
34*4882a593Smuzhiyun .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
35*4882a593Smuzhiyun .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
36*4882a593Smuzhiyun .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
37*4882a593Smuzhiyun .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
38*4882a593Smuzhiyun .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
39*4882a593Smuzhiyun .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
40*4882a593Smuzhiyun .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
41*4882a593Smuzhiyun .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
42*4882a593Smuzhiyun .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
43*4882a593Smuzhiyun .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
44*4882a593Smuzhiyun .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
45*4882a593Smuzhiyun .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
46*4882a593Smuzhiyun .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
47*4882a593Smuzhiyun .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
48*4882a593Smuzhiyun .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
49*4882a593Smuzhiyun .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
50*4882a593Smuzhiyun .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
51*4882a593Smuzhiyun .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun get_sys_info(&sysinfo);
55*4882a593Smuzhiyun printf("Configuring DDR for %s MT/s data rate\n",
56*4882a593Smuzhiyun strmhz(buf, sysinfo.freq_ddrbus));
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
63*4882a593Smuzhiyun ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
64*4882a593Smuzhiyun printf("ERROR setting Local Access Windows for DDR\n");
65*4882a593Smuzhiyun return 0;
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun return ddr_size;
69*4882a593Smuzhiyun }
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