1*4882a593SmuzhiyunOverview 2*4882a593Smuzhiyun-------- 3*4882a593SmuzhiyunP1_P2_RDB_PC represents a set of boards including 4*4882a593Smuzhiyun P1020MSBG-PC 5*4882a593Smuzhiyun P1020RDB-PC 6*4882a593Smuzhiyun P1020RDB-PD 7*4882a593Smuzhiyun P1020UTM-PC 8*4882a593Smuzhiyun P1021RDB-PC 9*4882a593Smuzhiyun P1024RDB 10*4882a593Smuzhiyun P1025RDB 11*4882a593Smuzhiyun P2020RDB-PC 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunThey have similar design of P1020RDB but have DDR3 instead of DDR2. P2020RDB-PC 14*4882a593Smuzhiyunhas 64-bit DDR. All others have 32-bit DDR. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunKey features on these boards include: 17*4882a593Smuzhiyun * DDR3 18*4882a593Smuzhiyun * NOR flash 19*4882a593Smuzhiyun * NAND flash (on RDB's only) 20*4882a593Smuzhiyun * SPI flash (on RDB's only) 21*4882a593Smuzhiyun * SDHC/MMC card slot 22*4882a593Smuzhiyun * VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB) 23*4882a593Smuzhiyun * PCIE slot and mini-PCIE slots 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunAs these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM 26*4882a593Smuzhiyunis used to store SPD data. In case of absent or corrupted SPD, falling back 27*4882a593Smuzhiyunto timing data embedded in the source code will be used. Raw timing data is 28*4882a593Smuzhiyunextracted from DDR chip datasheet. Different speeds of DDR are supported with 29*4882a593Smuzhiyunthis approach. ODT option is forced to fit this set of boards, again because 30*4882a593Smuzhiyunthey don't have regular DIMMs. 31*4882a593Smuzhiyun 32*4882a593SmuzhiyunCONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet specification 33*4882a593Smuzhiyunfor writing timing. 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunVSC firmware Address is defined by default in config file for eTSEC1. 36*4882a593Smuzhiyun 37*4882a593SmuzhiyunSD width is based off DIP switch. DIP switch is detected on the 38*4882a593Smuzhiyunboard by reading i2c bus and setting the appropriate mux values. 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunSome boards have QE module in the silicon (P1021 and P1025). QE and eLBC have 41*4882a593Smuzhiyunpins multiplexing. QE function needs to be disabled to access Nor Flash and 42*4882a593SmuzhiyunCPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe" 43*4882a593Smuzhiyunin hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to 44*4882a593Smuzhiyunenable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD. 47*4882a593Smuzhiyun'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD. 48