1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2013 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/mmu.h>
9*4882a593Smuzhiyun #include <asm/immap_85xx.h>
10*4882a593Smuzhiyun #include <asm/processor.h>
11*4882a593Smuzhiyun #include <fsl_ddr_sdram.h>
12*4882a593Smuzhiyun #include <fsl_ddr_dimm_params.h>
13*4882a593Smuzhiyun #include <asm/io.h>
14*4882a593Smuzhiyun #include <asm/fsl_law.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /* CONFIG_SYS_DDR_RAW_TIMING */
19*4882a593Smuzhiyun /*
20*4882a593Smuzhiyun * Hynix H5TQ1G83TFR-H9C
21*4882a593Smuzhiyun */
22*4882a593Smuzhiyun dimm_params_t ddr_raw_timing = {
23*4882a593Smuzhiyun .n_ranks = 1,
24*4882a593Smuzhiyun .rank_density = 536870912u,
25*4882a593Smuzhiyun .capacity = 536870912u,
26*4882a593Smuzhiyun .primary_sdram_width = 32,
27*4882a593Smuzhiyun .ec_sdram_width = 0,
28*4882a593Smuzhiyun .registered_dimm = 0,
29*4882a593Smuzhiyun .mirrored_dimm = 0,
30*4882a593Smuzhiyun .n_row_addr = 14,
31*4882a593Smuzhiyun .n_col_addr = 10,
32*4882a593Smuzhiyun .n_banks_per_sdram_device = 8,
33*4882a593Smuzhiyun .edc_config = 0,
34*4882a593Smuzhiyun .burst_lengths_bitmask = 0x0c,
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun .tckmin_x_ps = 1875,
37*4882a593Smuzhiyun .caslat_x = 0x1e << 4, /* 5,6,7,8 */
38*4882a593Smuzhiyun .taa_ps = 13125,
39*4882a593Smuzhiyun .twr_ps = 18000,
40*4882a593Smuzhiyun .trcd_ps = 13125,
41*4882a593Smuzhiyun .trrd_ps = 7500,
42*4882a593Smuzhiyun .trp_ps = 13125,
43*4882a593Smuzhiyun .tras_ps = 37500,
44*4882a593Smuzhiyun .trc_ps = 50625,
45*4882a593Smuzhiyun .trfc_ps = 160000,
46*4882a593Smuzhiyun .twtr_ps = 7500,
47*4882a593Smuzhiyun .trtp_ps = 7500,
48*4882a593Smuzhiyun .refresh_rate_ps = 7800000,
49*4882a593Smuzhiyun .tfaw_ps = 37500,
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun
fsl_ddr_get_dimm_params(dimm_params_t * pdimm,unsigned int controller_number,unsigned int dimm_number)52*4882a593Smuzhiyun int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
53*4882a593Smuzhiyun unsigned int controller_number,
54*4882a593Smuzhiyun unsigned int dimm_number)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun const char dimm_model[] = "Fixed DDR on board";
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun if ((controller_number == 0) && (dimm_number == 0)) {
59*4882a593Smuzhiyun memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
60*4882a593Smuzhiyun memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
61*4882a593Smuzhiyun memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun return 0;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)67*4882a593Smuzhiyun void fsl_ddr_board_options(memctl_options_t *popts,
68*4882a593Smuzhiyun dimm_params_t *pdimm,
69*4882a593Smuzhiyun unsigned int ctrl_num)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun int i;
72*4882a593Smuzhiyun popts->clk_adjust = 6;
73*4882a593Smuzhiyun popts->cpo_override = 0x1f;
74*4882a593Smuzhiyun popts->write_data_delay = 2;
75*4882a593Smuzhiyun popts->half_strength_driver_enable = 1;
76*4882a593Smuzhiyun /* Write leveling override */
77*4882a593Smuzhiyun popts->wrlvl_en = 1;
78*4882a593Smuzhiyun popts->wrlvl_override = 1;
79*4882a593Smuzhiyun popts->wrlvl_sample = 0xf;
80*4882a593Smuzhiyun popts->wrlvl_start = 0x8;
81*4882a593Smuzhiyun popts->trwt_override = 1;
82*4882a593Smuzhiyun popts->trwt = 0;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
85*4882a593Smuzhiyun popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
86*4882a593Smuzhiyun popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun }
89