1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2010 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
4*4882a593Smuzhiyun * Timur Tabi <timur@freescale.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <fsl_ddr_sdram.h>
12*4882a593Smuzhiyun #include <fsl_ddr_dimm_params.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun struct board_specific_parameters {
15*4882a593Smuzhiyun u32 n_ranks;
16*4882a593Smuzhiyun u32 datarate_mhz_high;
17*4882a593Smuzhiyun u32 clk_adjust; /* Range: 0-8 */
18*4882a593Smuzhiyun u32 cpo; /* Range: 2-31 */
19*4882a593Smuzhiyun u32 write_data_delay; /* Range: 0-6 */
20*4882a593Smuzhiyun u32 force_2t;
21*4882a593Smuzhiyun };
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /*
24*4882a593Smuzhiyun * This table contains all valid speeds we want to override with board
25*4882a593Smuzhiyun * specific parameters. datarate_mhz_high values need to be in ascending order
26*4882a593Smuzhiyun * for each n_ranks group.
27*4882a593Smuzhiyun */
28*4882a593Smuzhiyun static const struct board_specific_parameters dimm0[] = {
29*4882a593Smuzhiyun /*
30*4882a593Smuzhiyun * memory controller 0
31*4882a593Smuzhiyun * num| hi| clk| cpo|wrdata|2T
32*4882a593Smuzhiyun * ranks| mhz|adjst| | delay|
33*4882a593Smuzhiyun */
34*4882a593Smuzhiyun {1, 549, 5, 31, 3, 0},
35*4882a593Smuzhiyun {1, 850, 5, 31, 5, 0},
36*4882a593Smuzhiyun {2, 549, 5, 31, 3, 0},
37*4882a593Smuzhiyun {2, 850, 5, 31, 5, 0},
38*4882a593Smuzhiyun {}
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)41*4882a593Smuzhiyun void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
42*4882a593Smuzhiyun unsigned int ctrl_num)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
45*4882a593Smuzhiyun unsigned long ddr_freq;
46*4882a593Smuzhiyun unsigned int i;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun if (ctrl_num) {
50*4882a593Smuzhiyun printf("Wrong parameter for controller number %d", ctrl_num);
51*4882a593Smuzhiyun return;
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun if (!pdimm->n_ranks)
54*4882a593Smuzhiyun return;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /* set odt_rd_cfg and odt_wr_cfg. */
57*4882a593Smuzhiyun for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
58*4882a593Smuzhiyun popts->cs_local_opts[i].odt_rd_cfg = 0;
59*4882a593Smuzhiyun popts->cs_local_opts[i].odt_wr_cfg = 1;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun pbsp = dimm0;
63*4882a593Smuzhiyun /*
64*4882a593Smuzhiyun * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
65*4882a593Smuzhiyun * freqency and n_banks specified in board_specific_parameters table.
66*4882a593Smuzhiyun */
67*4882a593Smuzhiyun ddr_freq = get_ddr_freq(0) / 1000000;
68*4882a593Smuzhiyun while (pbsp->datarate_mhz_high) {
69*4882a593Smuzhiyun if (pbsp->n_ranks == pdimm->n_ranks) {
70*4882a593Smuzhiyun if (ddr_freq <= pbsp->datarate_mhz_high) {
71*4882a593Smuzhiyun popts->clk_adjust = pbsp->clk_adjust;
72*4882a593Smuzhiyun popts->cpo_override = pbsp->cpo;
73*4882a593Smuzhiyun popts->write_data_delay =
74*4882a593Smuzhiyun pbsp->write_data_delay;
75*4882a593Smuzhiyun popts->twot_en = pbsp->force_2t;
76*4882a593Smuzhiyun goto found;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun pbsp_highest = pbsp;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun pbsp++;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun if (pbsp_highest) {
84*4882a593Smuzhiyun printf("Error: board specific timing not found "
85*4882a593Smuzhiyun "for data rate %lu MT/s!\n"
86*4882a593Smuzhiyun "Trying to use the highest speed (%u) parameters\n",
87*4882a593Smuzhiyun ddr_freq, pbsp_highest->datarate_mhz_high);
88*4882a593Smuzhiyun popts->clk_adjust = pbsp->clk_adjust;
89*4882a593Smuzhiyun popts->cpo_override = pbsp->cpo;
90*4882a593Smuzhiyun popts->write_data_delay = pbsp->write_data_delay;
91*4882a593Smuzhiyun popts->twot_en = pbsp->force_2t;
92*4882a593Smuzhiyun } else {
93*4882a593Smuzhiyun panic("DIMM is not supported by this board");
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun found:
97*4882a593Smuzhiyun popts->half_strength_driver_enable = 1;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun /* Per AN4039, enable ZQ calibration. */
100*4882a593Smuzhiyun popts->zq_en = 1;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /*
103*4882a593Smuzhiyun * For wake-up on ARP, we need auto self refresh enabled
104*4882a593Smuzhiyun */
105*4882a593Smuzhiyun popts->auto_self_refresh_en = 1;
106*4882a593Smuzhiyun popts->sr_it = 0xb;
107*4882a593Smuzhiyun }
108