1*4882a593Smuzhiyun /* Copyright 2013 Freescale Semiconductor, Inc.
2*4882a593Smuzhiyun *
3*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <common.h>
7*4882a593Smuzhiyun #include <console.h>
8*4882a593Smuzhiyun #include <environment.h>
9*4882a593Smuzhiyun #include <ns16550.h>
10*4882a593Smuzhiyun #include <malloc.h>
11*4882a593Smuzhiyun #include <mmc.h>
12*4882a593Smuzhiyun #include <nand.h>
13*4882a593Smuzhiyun #include <i2c.h>
14*4882a593Smuzhiyun #include <fsl_esdhc.h>
15*4882a593Smuzhiyun #include <spi_flash.h>
16*4882a593Smuzhiyun #include "../common/spl.h"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
19*4882a593Smuzhiyun
get_effective_memsize(void)20*4882a593Smuzhiyun phys_size_t get_effective_memsize(void)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun return CONFIG_SYS_L2_SIZE;
23*4882a593Smuzhiyun }
24*4882a593Smuzhiyun
board_init_f(ulong bootflag)25*4882a593Smuzhiyun void board_init_f(ulong bootflag)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun u32 plat_ratio;
28*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
29*4882a593Smuzhiyun struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun console_init_f();
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* Clock configuration to access CPLD using IFC(GPCM) */
34*4882a593Smuzhiyun setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #ifdef CONFIG_TARGET_P1010RDB_PB
37*4882a593Smuzhiyun setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
38*4882a593Smuzhiyun #endif
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /* initialize selected port with appropriate baud rate */
41*4882a593Smuzhiyun plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
42*4882a593Smuzhiyun plat_ratio >>= 1;
43*4882a593Smuzhiyun gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
46*4882a593Smuzhiyun gd->bus_clk / 16 / CONFIG_BAUDRATE);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #ifdef CONFIG_SPL_MMC_BOOT
49*4882a593Smuzhiyun puts("\nSD boot...\n");
50*4882a593Smuzhiyun #elif defined(CONFIG_SPL_SPI_BOOT)
51*4882a593Smuzhiyun puts("\nSPI Flash boot...\n");
52*4882a593Smuzhiyun #endif
53*4882a593Smuzhiyun /* copy code to RAM and jump to it - this should not return */
54*4882a593Smuzhiyun /* NOTE - code has to be copied out of NAND buffer before
55*4882a593Smuzhiyun * other blocks can be read.
56*4882a593Smuzhiyun */
57*4882a593Smuzhiyun relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
board_init_r(gd_t * gd,ulong dest_addr)60*4882a593Smuzhiyun void board_init_r(gd_t *gd, ulong dest_addr)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun /* Pointer is writable since we allocated a register for it */
63*4882a593Smuzhiyun gd = (gd_t *)CONFIG_SPL_GD_ADDR;
64*4882a593Smuzhiyun bd_t *bd;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun memset(gd, 0, sizeof(gd_t));
67*4882a593Smuzhiyun bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
68*4882a593Smuzhiyun memset(bd, 0, sizeof(bd_t));
69*4882a593Smuzhiyun gd->bd = bd;
70*4882a593Smuzhiyun bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
71*4882a593Smuzhiyun bd->bi_memsize = CONFIG_SYS_L2_SIZE;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun arch_cpu_init();
74*4882a593Smuzhiyun get_clocks();
75*4882a593Smuzhiyun mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
76*4882a593Smuzhiyun CONFIG_SPL_RELOC_MALLOC_SIZE);
77*4882a593Smuzhiyun gd->flags |= GD_FLG_FULL_MALLOC_INIT;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun #ifndef CONFIG_SPL_NAND_BOOT
80*4882a593Smuzhiyun env_init();
81*4882a593Smuzhiyun #endif
82*4882a593Smuzhiyun #ifdef CONFIG_SPL_MMC_BOOT
83*4882a593Smuzhiyun mmc_initialize(bd);
84*4882a593Smuzhiyun #endif
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun /* relocate environment function pointers etc. */
87*4882a593Smuzhiyun #ifdef CONFIG_SPL_NAND_BOOT
88*4882a593Smuzhiyun nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
89*4882a593Smuzhiyun (uchar *)CONFIG_ENV_ADDR);
90*4882a593Smuzhiyun gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
91*4882a593Smuzhiyun gd->env_valid = ENV_VALID;
92*4882a593Smuzhiyun #else
93*4882a593Smuzhiyun env_relocate();
94*4882a593Smuzhiyun #endif
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun i2c_init_all();
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun dram_init();
99*4882a593Smuzhiyun #ifdef CONFIG_SPL_NAND_BOOT
100*4882a593Smuzhiyun puts("\nTertiary program loader running in sram...");
101*4882a593Smuzhiyun #else
102*4882a593Smuzhiyun puts("\nSecond program loader running in sram...");
103*4882a593Smuzhiyun #endif
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun #ifdef CONFIG_SPL_MMC_BOOT
106*4882a593Smuzhiyun mmc_boot();
107*4882a593Smuzhiyun #elif defined(CONFIG_SPL_SPI_BOOT)
108*4882a593Smuzhiyun fsl_spi_boot();
109*4882a593Smuzhiyun #elif defined(CONFIG_SPL_NAND_BOOT)
110*4882a593Smuzhiyun nand_boot();
111*4882a593Smuzhiyun #endif
112*4882a593Smuzhiyun }
113