1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2016 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <asm/arch/clock.h>
8*4882a593Smuzhiyun #include <asm/arch/iomux.h>
9*4882a593Smuzhiyun #include <asm/arch/imx-regs.h>
10*4882a593Smuzhiyun #include <asm/arch/crm_regs.h>
11*4882a593Smuzhiyun #include <asm/arch/mx6-pins.h>
12*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
13*4882a593Smuzhiyun #include <asm/gpio.h>
14*4882a593Smuzhiyun #include <asm/mach-imx/iomux-v3.h>
15*4882a593Smuzhiyun #include <asm/mach-imx/boot_mode.h>
16*4882a593Smuzhiyun #include <asm/io.h>
17*4882a593Smuzhiyun #include <common.h>
18*4882a593Smuzhiyun #include <fsl_esdhc.h>
19*4882a593Smuzhiyun #include <linux/sizes.h>
20*4882a593Smuzhiyun #include <mmc.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
25*4882a593Smuzhiyun PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
26*4882a593Smuzhiyun PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
27*4882a593Smuzhiyun
dram_init(void)28*4882a593Smuzhiyun int dram_init(void)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun gd->ram_size = imx_ddr_size();
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun return 0;
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun static iomux_v3_cfg_t const uart1_pads[] = {
36*4882a593Smuzhiyun MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
37*4882a593Smuzhiyun MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun
setup_iomux_uart(void)40*4882a593Smuzhiyun static void setup_iomux_uart(void)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
board_mmc_get_env_dev(int devno)45*4882a593Smuzhiyun int board_mmc_get_env_dev(int devno)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun return devno;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
mmc_map_to_kernel_blk(int devno)50*4882a593Smuzhiyun int mmc_map_to_kernel_blk(int devno)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun return devno;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
board_early_init_f(void)55*4882a593Smuzhiyun int board_early_init_f(void)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun setup_iomux_uart();
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun return 0;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
board_init(void)62*4882a593Smuzhiyun int board_init(void)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun /* Address of boot parameters */
65*4882a593Smuzhiyun gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun return 0;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun #ifdef CONFIG_CMD_BMODE
71*4882a593Smuzhiyun static const struct boot_mode board_boot_modes[] = {
72*4882a593Smuzhiyun /* 4 bit bus width */
73*4882a593Smuzhiyun {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
74*4882a593Smuzhiyun {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
75*4882a593Smuzhiyun {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
76*4882a593Smuzhiyun {NULL, 0},
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun #endif
79*4882a593Smuzhiyun
board_late_init(void)80*4882a593Smuzhiyun int board_late_init(void)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun #ifdef CONFIG_CMD_BMODE
83*4882a593Smuzhiyun add_board_boot_modes(board_boot_modes);
84*4882a593Smuzhiyun #endif
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
87*4882a593Smuzhiyun env_set("board_name", "EVK");
88*4882a593Smuzhiyun env_set("board_rev", "14X14");
89*4882a593Smuzhiyun #endif
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun return 0;
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
checkboard(void)94*4882a593Smuzhiyun int checkboard(void)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun puts("Board: MX6ULL 14x14 EVK\n");
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun return 0;
99*4882a593Smuzhiyun }
100