1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2014 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#define __ASSEMBLY__ 8*4882a593Smuzhiyun#include <config.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/* image version */ 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunIMAGE_VERSION 2 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun/* 15*4882a593Smuzhiyun * Boot Device : one of 16*4882a593Smuzhiyun * spi/sd/nand/onenand, qspi/nor 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunBOOT_FROM sd 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun/* 22*4882a593Smuzhiyun * Device Configuration Data (DCD) 23*4882a593Smuzhiyun * 24*4882a593Smuzhiyun * Each entry must have the format: 25*4882a593Smuzhiyun * Addr-type Address Value 26*4882a593Smuzhiyun * 27*4882a593Smuzhiyun * where: 28*4882a593Smuzhiyun * Addr-type register length (1,2 or 4 bytes) 29*4882a593Smuzhiyun * Address absolute address of the register 30*4882a593Smuzhiyun * value value to be stored in the register 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun/* Enable all clocks */ 34*4882a593SmuzhiyunDATA 4 0x020c4068 0xffffffff 35*4882a593SmuzhiyunDATA 4 0x020c406c 0xffffffff 36*4882a593SmuzhiyunDATA 4 0x020c4070 0xffffffff 37*4882a593SmuzhiyunDATA 4 0x020c4074 0xffffffff 38*4882a593SmuzhiyunDATA 4 0x020c4078 0xffffffff 39*4882a593SmuzhiyunDATA 4 0x020c407c 0xffffffff 40*4882a593SmuzhiyunDATA 4 0x020c4080 0xffffffff 41*4882a593SmuzhiyunDATA 4 0x020c4084 0xffffffff 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun/* IOMUX - DDR IO Type */ 44*4882a593SmuzhiyunDATA 4 0x020e0618 0x000c0000 45*4882a593SmuzhiyunDATA 4 0x020e05fc 0x00000000 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun/* Clock */ 48*4882a593SmuzhiyunDATA 4 0x020e032c 0x00000030 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun/* Address */ 51*4882a593SmuzhiyunDATA 4 0x020e0300 0x00000030 52*4882a593SmuzhiyunDATA 4 0x020e02fc 0x00000030 53*4882a593SmuzhiyunDATA 4 0x020e05f4 0x00000030 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun/* Control */ 56*4882a593SmuzhiyunDATA 4 0x020e0340 0x00000030 57*4882a593Smuzhiyun 58*4882a593SmuzhiyunDATA 4 0x020e0320 0x00000000 59*4882a593SmuzhiyunDATA 4 0x020e0310 0x00000030 60*4882a593SmuzhiyunDATA 4 0x020e0314 0x00000030 61*4882a593SmuzhiyunDATA 4 0x020e0614 0x00000030 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun/* Data Strobe */ 64*4882a593SmuzhiyunDATA 4 0x020e05f8 0x00020000 65*4882a593SmuzhiyunDATA 4 0x020e0330 0x00000030 66*4882a593SmuzhiyunDATA 4 0x020e0334 0x00000030 67*4882a593SmuzhiyunDATA 4 0x020e0338 0x00000030 68*4882a593SmuzhiyunDATA 4 0x020e033c 0x00000030 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun/* Data */ 71*4882a593SmuzhiyunDATA 4 0x020e0608 0x00020000 72*4882a593SmuzhiyunDATA 4 0x020e060c 0x00000030 73*4882a593SmuzhiyunDATA 4 0x020e0610 0x00000030 74*4882a593SmuzhiyunDATA 4 0x020e061c 0x00000030 75*4882a593SmuzhiyunDATA 4 0x020e0620 0x00000030 76*4882a593SmuzhiyunDATA 4 0x020e02ec 0x00000030 77*4882a593SmuzhiyunDATA 4 0x020e02f0 0x00000030 78*4882a593SmuzhiyunDATA 4 0x020e02f4 0x00000030 79*4882a593SmuzhiyunDATA 4 0x020e02f8 0x00000030 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun/* Calibrations - ZQ */ 82*4882a593SmuzhiyunDATA 4 0x021b0800 0xa1390003 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun/* Write leveling */ 85*4882a593SmuzhiyunDATA 4 0x021b080c 0x002C003D 86*4882a593SmuzhiyunDATA 4 0x021b0810 0x00110046 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun/* DQS Read Gate */ 89*4882a593SmuzhiyunDATA 4 0x021b083c 0x4160016C 90*4882a593SmuzhiyunDATA 4 0x021b0840 0x013C016C 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun/* Read/Write Delay */ 93*4882a593SmuzhiyunDATA 4 0x021b0848 0x46424446 94*4882a593SmuzhiyunDATA 4 0x021b0850 0x3A3C3C3A 95*4882a593Smuzhiyun 96*4882a593SmuzhiyunDATA 4 0x021b08c0 0x2492244A 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun/* read data bit delay */ 99*4882a593SmuzhiyunDATA 4 0x021b081c 0x33333333 100*4882a593SmuzhiyunDATA 4 0x021b0820 0x33333333 101*4882a593SmuzhiyunDATA 4 0x021b0824 0x33333333 102*4882a593SmuzhiyunDATA 4 0x021b0828 0x33333333 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun/* Complete calibration by forced measurement */ 105*4882a593SmuzhiyunDATA 4 0x021b08b8 0x00000800 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */ 108*4882a593SmuzhiyunDATA 4 0x021b0004 0x0002002d 109*4882a593SmuzhiyunDATA 4 0x021b0008 0x00333030 110*4882a593SmuzhiyunDATA 4 0x021b000c 0x676b52f3 111*4882a593SmuzhiyunDATA 4 0x021b0010 0xb66d8b63 112*4882a593SmuzhiyunDATA 4 0x021b0014 0x01ff00db 113*4882a593SmuzhiyunDATA 4 0x021b0018 0x00011740 114*4882a593SmuzhiyunDATA 4 0x021b001c 0x00008000 115*4882a593SmuzhiyunDATA 4 0x021b002c 0x000026d2 116*4882a593SmuzhiyunDATA 4 0x021b0030 0x006b1023 117*4882a593SmuzhiyunDATA 4 0x021b0040 0x0000007f 118*4882a593SmuzhiyunDATA 4 0x021b0000 0x85190000 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun/* Initialize MT41K256M16HA-125 - MR2 */ 121*4882a593SmuzhiyunDATA 4 0x021b001c 0x04008032 122*4882a593Smuzhiyun/* MR3 */ 123*4882a593SmuzhiyunDATA 4 0x021b001c 0x00008033 124*4882a593Smuzhiyun/* MR1 */ 125*4882a593SmuzhiyunDATA 4 0x021b001c 0x00068031 126*4882a593Smuzhiyun/* MR0 */ 127*4882a593SmuzhiyunDATA 4 0x021b001c 0x05208030 128*4882a593Smuzhiyun/* DDR device ZQ calibration */ 129*4882a593SmuzhiyunDATA 4 0x021b001c 0x04008040 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun/* Final DDR setup, before operation start */ 132*4882a593SmuzhiyunDATA 4 0x021b0020 0x00000800 133*4882a593SmuzhiyunDATA 4 0x021b0818 0x00022227 134*4882a593SmuzhiyunDATA 4 0x021b0004 0x0002556d 135*4882a593SmuzhiyunDATA 4 0x021b0404 0x00011006 136*4882a593SmuzhiyunDATA 4 0x021b001c 0x00000000 137