1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2016 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <asm/arch/clock.h>
8*4882a593Smuzhiyun #include <asm/arch/crm_regs.h>
9*4882a593Smuzhiyun #include <asm/arch/iomux.h>
10*4882a593Smuzhiyun #include <asm/arch/imx-regs.h>
11*4882a593Smuzhiyun #include <asm/arch/mx6-pins.h>
12*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
13*4882a593Smuzhiyun #include <asm/gpio.h>
14*4882a593Smuzhiyun #include <asm/mach-imx/iomux-v3.h>
15*4882a593Smuzhiyun #include <asm/mach-imx/boot_mode.h>
16*4882a593Smuzhiyun #include <asm/io.h>
17*4882a593Smuzhiyun #include <common.h>
18*4882a593Smuzhiyun #include <linux/sizes.h>
19*4882a593Smuzhiyun #include <mmc.h>
20*4882a593Smuzhiyun #include <power/pmic.h>
21*4882a593Smuzhiyun #include <power/pfuze100_pmic.h>
22*4882a593Smuzhiyun #include "../common/pfuze.h"
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
27*4882a593Smuzhiyun PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
28*4882a593Smuzhiyun PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
29*4882a593Smuzhiyun
dram_init(void)30*4882a593Smuzhiyun int dram_init(void)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun gd->ram_size = imx_ddr_size();
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun return 0;
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun static iomux_v3_cfg_t const uart1_pads[] = {
38*4882a593Smuzhiyun MX6_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
39*4882a593Smuzhiyun MX6_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun static iomux_v3_cfg_t const wdog_pads[] = {
43*4882a593Smuzhiyun MX6_PAD_WDOG_B__WDOG1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun
setup_iomux_uart(void)46*4882a593Smuzhiyun static void setup_iomux_uart(void)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun #ifdef CONFIG_DM_PMIC_PFUZE100
power_init_board(void)52*4882a593Smuzhiyun int power_init_board(void)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun struct udevice *dev;
55*4882a593Smuzhiyun int ret;
56*4882a593Smuzhiyun u32 dev_id, rev_id, i;
57*4882a593Smuzhiyun u32 switch_num = 6;
58*4882a593Smuzhiyun u32 offset = PFUZE100_SW1CMODE;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun ret = pmic_get("pfuze100", &dev);
61*4882a593Smuzhiyun if (ret == -ENODEV)
62*4882a593Smuzhiyun return 0;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun if (ret != 0)
65*4882a593Smuzhiyun return ret;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
68*4882a593Smuzhiyun rev_id = pmic_reg_read(dev, PFUZE100_REVID);
69*4882a593Smuzhiyun printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /* Init mode to APS_PFM */
73*4882a593Smuzhiyun pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun for (i = 0; i < switch_num - 1; i++)
76*4882a593Smuzhiyun pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /* set SW1AB staby volatage 0.975V */
79*4882a593Smuzhiyun pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
82*4882a593Smuzhiyun pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* set SW1C staby volatage 0.975V */
85*4882a593Smuzhiyun pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
88*4882a593Smuzhiyun pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun return 0;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun #endif
93*4882a593Smuzhiyun
board_early_init_f(void)94*4882a593Smuzhiyun int board_early_init_f(void)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun setup_iomux_uart();
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun return 0;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
board_init(void)101*4882a593Smuzhiyun int board_init(void)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun /* Address of boot parameters */
104*4882a593Smuzhiyun gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun return 0;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
board_late_init(void)109*4882a593Smuzhiyun int board_late_init(void)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun return 0;
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun
checkboard(void)116*4882a593Smuzhiyun int checkboard(void)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun puts("Board: MX6SLL EVK\n");
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun return 0;
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
board_mmc_get_env_dev(int devno)123*4882a593Smuzhiyun int board_mmc_get_env_dev(int devno)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun return devno;
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun
mmc_map_to_kernel_blk(int devno)128*4882a593Smuzhiyun int mmc_map_to_kernel_blk(int devno)
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun return devno;
131*4882a593Smuzhiyun }
132