1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * (C Copyright 2009 3*4882a593Smuzhiyun * Stefano Babic DENX Software Engineering sbabic@denx.de. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Refer doc/README.imximage for more details about how-to configure 8*4882a593Smuzhiyun * and create imximage boot image 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * The syntax is taken as close as possible with the kwbimage 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/* 14*4882a593Smuzhiyun * Boot Device : one of 15*4882a593Smuzhiyun * spi, sd (the board has no nand neither onenand) 16*4882a593Smuzhiyun */ 17*4882a593SmuzhiyunBOOT_FROM spi 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun/* 20*4882a593Smuzhiyun * Device Configuration Data (DCD) 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * Each entry must have the format: 23*4882a593Smuzhiyun * Addr-type Address Value 24*4882a593Smuzhiyun * 25*4882a593Smuzhiyun * where: 26*4882a593Smuzhiyun * Addr-type register length (1,2 or 4 bytes) 27*4882a593Smuzhiyun * Address absolute address of the register 28*4882a593Smuzhiyun * value value to be stored in the register 29*4882a593Smuzhiyun */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun/* Setting IOMUXC */ 32*4882a593SmuzhiyunDATA 4 0x73FA88a0 0x200 33*4882a593SmuzhiyunDATA 4 0x73FA850c 0x20c5 34*4882a593SmuzhiyunDATA 4 0x73FA8510 0x20c5 35*4882a593SmuzhiyunDATA 4 0x73FA883c 0x2 36*4882a593SmuzhiyunDATA 4 0x73FA8848 0x2 37*4882a593SmuzhiyunDATA 4 0x73FA84b8 0xe7 38*4882a593SmuzhiyunDATA 4 0x73FA84bc 0x45 39*4882a593SmuzhiyunDATA 4 0x73FA84c0 0x45 40*4882a593SmuzhiyunDATA 4 0x73FA84c4 0x45 41*4882a593SmuzhiyunDATA 4 0x73FA84c8 0x45 42*4882a593SmuzhiyunDATA 4 0x73FA8820 0x0 43*4882a593SmuzhiyunDATA 4 0x73FA84a4 0x3 44*4882a593SmuzhiyunDATA 4 0x73FA84a8 0x3 45*4882a593SmuzhiyunDATA 4 0x73FA84ac 0xe3 46*4882a593SmuzhiyunDATA 4 0x73FA84b0 0xe3 47*4882a593SmuzhiyunDATA 4 0x73FA84b4 0xe3 48*4882a593SmuzhiyunDATA 4 0x73FA84cc 0xe3 49*4882a593SmuzhiyunDATA 4 0x73FA84d0 0xe2 50*4882a593Smuzhiyun 51*4882a593SmuzhiyunDATA 4 0x73FA882c 0x6 52*4882a593SmuzhiyunDATA 4 0x73FA88a4 0x6 53*4882a593SmuzhiyunDATA 4 0x73FA88ac 0x6 54*4882a593SmuzhiyunDATA 4 0x73FA88b8 0x6 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun/* 57*4882a593Smuzhiyun * Setting DDR for micron 58*4882a593Smuzhiyun * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model 59*4882a593Smuzhiyun * CAS=3 BL=4 60*4882a593Smuzhiyun */ 61*4882a593Smuzhiyun/* ESDCTL_ESDCTL0 */ 62*4882a593SmuzhiyunDATA 4 0x83FD9000 0x82a20000 63*4882a593Smuzhiyun/* ESDCTL_ESDCTL1 */ 64*4882a593SmuzhiyunDATA 4 0x83FD9008 0x82a20000 65*4882a593Smuzhiyun/* ESDCTL_ESDMISC */ 66*4882a593SmuzhiyunDATA 4 0x83FD9010 0x000ad0d0 67*4882a593Smuzhiyun/* ESDCTL_ESDCFG0 */ 68*4882a593SmuzhiyunDATA 4 0x83FD9004 0x333574aa 69*4882a593Smuzhiyun/* ESDCTL_ESDCFG1 */ 70*4882a593SmuzhiyunDATA 4 0x83FD900C 0x333574aa 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun/* Init DRAM on CS0 */ 73*4882a593Smuzhiyun/* ESDCTL_ESDSCR */ 74*4882a593SmuzhiyunDATA 4 0x83FD9014 0x04008008 75*4882a593SmuzhiyunDATA 4 0x83FD9014 0x0000801a 76*4882a593SmuzhiyunDATA 4 0x83FD9014 0x0000801b 77*4882a593SmuzhiyunDATA 4 0x83FD9014 0x00448019 78*4882a593SmuzhiyunDATA 4 0x83FD9014 0x07328018 79*4882a593SmuzhiyunDATA 4 0x83FD9014 0x04008008 80*4882a593SmuzhiyunDATA 4 0x83FD9014 0x00008010 81*4882a593SmuzhiyunDATA 4 0x83FD9014 0x00008010 82*4882a593SmuzhiyunDATA 4 0x83FD9014 0x06328018 83*4882a593SmuzhiyunDATA 4 0x83FD9014 0x03808019 84*4882a593SmuzhiyunDATA 4 0x83FD9014 0x00408019 85*4882a593SmuzhiyunDATA 4 0x83FD9014 0x00008000 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun/* Init DRAM on CS1 */ 88*4882a593SmuzhiyunDATA 4 0x83FD9014 0x0400800c 89*4882a593SmuzhiyunDATA 4 0x83FD9014 0x0000801e 90*4882a593SmuzhiyunDATA 4 0x83FD9014 0x0000801f 91*4882a593SmuzhiyunDATA 4 0x83FD9014 0x0000801d 92*4882a593SmuzhiyunDATA 4 0x83FD9014 0x0732801c 93*4882a593SmuzhiyunDATA 4 0x83FD9014 0x0400800c 94*4882a593SmuzhiyunDATA 4 0x83FD9014 0x00008014 95*4882a593SmuzhiyunDATA 4 0x83FD9014 0x00008014 96*4882a593SmuzhiyunDATA 4 0x83FD9014 0x0632801c 97*4882a593SmuzhiyunDATA 4 0x83FD9014 0x0380801d 98*4882a593SmuzhiyunDATA 4 0x83FD9014 0x0040801d 99*4882a593SmuzhiyunDATA 4 0x83FD9014 0x00008004 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun/* Write to CTL0 */ 102*4882a593SmuzhiyunDATA 4 0x83FD9000 0xb2a20000 103*4882a593Smuzhiyun/* Write to CTL1 */ 104*4882a593SmuzhiyunDATA 4 0x83FD9008 0xb2a20000 105*4882a593Smuzhiyun/* ESDMISC */ 106*4882a593SmuzhiyunDATA 4 0x83FD9010 0x000ad6d0 107*4882a593Smuzhiyun/* ESDCTL_ESDCDLYGD */ 108*4882a593SmuzhiyunDATA 4 0x83FD9034 0x90000000 109*4882a593SmuzhiyunDATA 4 0x83FD9014 0x00000000 110