1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __BOARD_MX35_3STACK_H 11*4882a593Smuzhiyun #define __BOARD_MX35_3STACK_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define DBG_BASE_ADDR WEIM_CTRL_CS5 14*4882a593Smuzhiyun #define DBG_CSCR_U_CONFIG 0x0000D843 15*4882a593Smuzhiyun #define DBG_CSCR_L_CONFIG 0x22252521 16*4882a593Smuzhiyun #define DBG_CSCR_A_CONFIG 0x22220A00 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define CCM_CCMR_CONFIG 0x003F4208 19*4882a593Smuzhiyun #define CCM_PDR0_CONFIG 0x00801000 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* MEMORY SETTING */ 22*4882a593Smuzhiyun #define ESDCTL_0x92220000 0x92220000 23*4882a593Smuzhiyun #define ESDCTL_0xA2220000 0xA2220000 24*4882a593Smuzhiyun #define ESDCTL_0xB2220000 0xB2220000 25*4882a593Smuzhiyun #define ESDCTL_0x82228080 0x82228080 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define ESDCTL_PRECHARGE 0x00000400 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define ESDCTL_MDDR_CONFIG 0x007FFC3F 30*4882a593Smuzhiyun #define ESDCTL_MDDR_MR 0x00000033 31*4882a593Smuzhiyun #define ESDCTL_MDDR_EMR 0x02000000 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define ESDCTL_DDR2_CONFIG 0x007FFC3F 34*4882a593Smuzhiyun #define ESDCTL_DDR2_EMR2 0x04000000 35*4882a593Smuzhiyun #define ESDCTL_DDR2_EMR3 0x06000000 36*4882a593Smuzhiyun #define ESDCTL_DDR2_EN_DLL 0x02000400 37*4882a593Smuzhiyun #define ESDCTL_DDR2_RESET_DLL 0x00000333 38*4882a593Smuzhiyun #define ESDCTL_DDR2_MR 0x00000233 39*4882a593Smuzhiyun #define ESDCTL_DDR2_OCD_DEFAULT 0x02000780 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define ESDCTL_DELAY_LINE5 0x00F49F00 42*4882a593Smuzhiyun #endif /* __BOARD_MX35_3STACK_H */ 43