1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include <config.h> 10*4882a593Smuzhiyun#include <asm/arch/imx-regs.h> 11*4882a593Smuzhiyun#include <generated/asm-offsets.h> 12*4882a593Smuzhiyun#include "mx35pdk.h" 13*4882a593Smuzhiyun#include <asm/arch/lowlevel_macro.S> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun/* 16*4882a593Smuzhiyun * return soc version 17*4882a593Smuzhiyun * 0x10: TO1 18*4882a593Smuzhiyun * 0x20: TO2 19*4882a593Smuzhiyun * 0x30: TO3 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun.macro check_soc_version ret, tmp 22*4882a593Smuzhiyun ldr \tmp, =IIM_BASE_ADDR 23*4882a593Smuzhiyun ldr \ret, [\tmp, #IIM_SREV] 24*4882a593Smuzhiyun cmp \ret, #0x00 25*4882a593Smuzhiyun moveq \tmp, #ROMPATCH_REV 26*4882a593Smuzhiyun ldreq \ret, [\tmp] 27*4882a593Smuzhiyun moveq \ret, \ret, lsl #4 28*4882a593Smuzhiyun addne \ret, \ret, #0x10 29*4882a593Smuzhiyun.endm 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun/* CPLD on CS5 setup */ 32*4882a593Smuzhiyun.macro init_debug_board 33*4882a593Smuzhiyun ldr r0, =DBG_BASE_ADDR 34*4882a593Smuzhiyun ldr r1, =DBG_CSCR_U_CONFIG 35*4882a593Smuzhiyun str r1, [r0, #0x00] 36*4882a593Smuzhiyun ldr r1, =DBG_CSCR_L_CONFIG 37*4882a593Smuzhiyun str r1, [r0, #0x04] 38*4882a593Smuzhiyun ldr r1, =DBG_CSCR_A_CONFIG 39*4882a593Smuzhiyun str r1, [r0, #0x08] 40*4882a593Smuzhiyun.endm 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun/* clock setup */ 43*4882a593Smuzhiyun.macro init_clock 44*4882a593Smuzhiyun ldr r0, =CCM_BASE_ADDR 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* default CLKO to 1/32 of the ARM core*/ 47*4882a593Smuzhiyun ldr r1, [r0, #CLKCTL_COSR] 48*4882a593Smuzhiyun bic r1, r1, #0x00000FF00 49*4882a593Smuzhiyun bic r1, r1, #0x0000000FF 50*4882a593Smuzhiyun mov r2, #0x00006C00 51*4882a593Smuzhiyun add r2, r2, #0x67 52*4882a593Smuzhiyun orr r1, r1, r2 53*4882a593Smuzhiyun str r1, [r0, #CLKCTL_COSR] 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun ldr r2, =CCM_CCMR_CONFIG 56*4882a593Smuzhiyun str r2, [r0, #CLKCTL_CCMR] 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun check_soc_version r1, r2 59*4882a593Smuzhiyun cmp r1, #CHIP_REV_2_0 60*4882a593Smuzhiyun ldrhs r3, =CCM_MPLL_532_HZ 61*4882a593Smuzhiyun bhs 1f 62*4882a593Smuzhiyun ldr r2, [r0, #CLKCTL_PDR0] 63*4882a593Smuzhiyun tst r2, #CLKMODE_CONSUMER 64*4882a593Smuzhiyun ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/ 65*4882a593Smuzhiyun ldreq r3, =CCM_MPLL_399_HZ /* auto path*/ 66*4882a593Smuzhiyun1: 67*4882a593Smuzhiyun str r3, [r0, #CLKCTL_MPCTL] 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun ldr r1, =CCM_PPLL_300_HZ 70*4882a593Smuzhiyun str r1, [r0, #CLKCTL_PPCTL] 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun ldr r1, =CCM_PDR0_CONFIG 73*4882a593Smuzhiyun bic r1, r1, #0x800000 74*4882a593Smuzhiyun str r1, [r0, #CLKCTL_PDR0] 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun ldr r1, [r0, #CLKCTL_CGR0] 77*4882a593Smuzhiyun orr r1, r1, #0x0C300000 78*4882a593Smuzhiyun str r1, [r0, #CLKCTL_CGR0] 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun ldr r1, [r0, #CLKCTL_CGR1] 81*4882a593Smuzhiyun orr r1, r1, #0x00000C00 82*4882a593Smuzhiyun orr r1, r1, #0x00000003 83*4882a593Smuzhiyun str r1, [r0, #CLKCTL_CGR1] 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun ldr r1, [r0, #CLKCTL_CGR2] 86*4882a593Smuzhiyun orr r1, r1, #0x00C00000 87*4882a593Smuzhiyun str r1, [r0, #CLKCTL_CGR2] 88*4882a593Smuzhiyun.endm 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun.macro setup_sdram 91*4882a593Smuzhiyun ldr r0, =ESDCTL_BASE_ADDR 92*4882a593Smuzhiyun mov r3, #0x2000 93*4882a593Smuzhiyun str r3, [r0, #0x0] 94*4882a593Smuzhiyun str r3, [r0, #0x8] 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /*ip(r12) has used to save lr register in upper calling*/ 97*4882a593Smuzhiyun mov fp, lr 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun mov r5, #0x00 100*4882a593Smuzhiyun mov r2, #0x00 101*4882a593Smuzhiyun mov r1, #CSD0_BASE_ADDR 102*4882a593Smuzhiyun bl setup_sdram_bank 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun mov r5, #0x00 105*4882a593Smuzhiyun mov r2, #0x00 106*4882a593Smuzhiyun mov r1, #CSD1_BASE_ADDR 107*4882a593Smuzhiyun bl setup_sdram_bank 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun mov lr, fp 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun1: 112*4882a593Smuzhiyun ldr r3, =ESDCTL_DELAY_LINE5 113*4882a593Smuzhiyun str r3, [r0, #0x30] 114*4882a593Smuzhiyun.endm 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun.globl lowlevel_init 117*4882a593Smuzhiyunlowlevel_init: 118*4882a593Smuzhiyun mov r10, lr 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun core_init 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun init_aips 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun init_max 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun init_m3if 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun init_clock 129*4882a593Smuzhiyun init_debug_board 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun cmp pc, #PHYS_SDRAM_1 132*4882a593Smuzhiyun blo init_sdram_start 133*4882a593Smuzhiyun cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) 134*4882a593Smuzhiyun blo skip_sdram_setup 135*4882a593Smuzhiyun 136*4882a593Smuzhiyuninit_sdram_start: 137*4882a593Smuzhiyun /*init_sdram*/ 138*4882a593Smuzhiyun setup_sdram 139*4882a593Smuzhiyun 140*4882a593Smuzhiyunskip_sdram_setup: 141*4882a593Smuzhiyun mov lr, r10 142*4882a593Smuzhiyun mov pc, lr 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun/* 146*4882a593Smuzhiyun * r0: ESDCTL control base, r1: sdram slot base 147*4882a593Smuzhiyun * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base 148*4882a593Smuzhiyun */ 149*4882a593Smuzhiyunsetup_sdram_bank: 150*4882a593Smuzhiyun mov r3, #0xE 151*4882a593Smuzhiyun tst r2, #0x1 152*4882a593Smuzhiyun orreq r3, r3, #0x300 /*DDR2*/ 153*4882a593Smuzhiyun str r3, [r0, #0x10] 154*4882a593Smuzhiyun bic r3, r3, #0x00A 155*4882a593Smuzhiyun str r3, [r0, #0x10] 156*4882a593Smuzhiyun beq 2f 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun mov r3, #0x20000 159*4882a593Smuzhiyun1: subs r3, r3, #1 160*4882a593Smuzhiyun bne 1b 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun2: tst r2, #0x1 163*4882a593Smuzhiyun ldreq r3, =ESDCTL_DDR2_CONFIG 164*4882a593Smuzhiyun ldrne r3, =ESDCTL_MDDR_CONFIG 165*4882a593Smuzhiyun cmp r1, #CSD1_BASE_ADDR 166*4882a593Smuzhiyun strlo r3, [r0, #0x4] 167*4882a593Smuzhiyun strhs r3, [r0, #0xC] 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun ldr r3, =ESDCTL_0x92220000 170*4882a593Smuzhiyun strlo r3, [r0, #0x0] 171*4882a593Smuzhiyun strhs r3, [r0, #0x8] 172*4882a593Smuzhiyun mov r3, #0xDA 173*4882a593Smuzhiyun ldr r4, =ESDCTL_PRECHARGE 174*4882a593Smuzhiyun strb r3, [r1, r4] 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun tst r2, #0x1 177*4882a593Smuzhiyun bne skip_set_mode 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun cmp r1, #CSD1_BASE_ADDR 180*4882a593Smuzhiyun ldr r3, =ESDCTL_0xB2220000 181*4882a593Smuzhiyun strlo r3, [r0, #0x0] 182*4882a593Smuzhiyun strhs r3, [r0, #0x8] 183*4882a593Smuzhiyun mov r3, #0xDA 184*4882a593Smuzhiyun ldr r4, =ESDCTL_DDR2_EMR2 185*4882a593Smuzhiyun strb r3, [r1, r4] 186*4882a593Smuzhiyun ldr r4, =ESDCTL_DDR2_EMR3 187*4882a593Smuzhiyun strb r3, [r1, r4] 188*4882a593Smuzhiyun ldr r4, =ESDCTL_DDR2_EN_DLL 189*4882a593Smuzhiyun strb r3, [r1, r4] 190*4882a593Smuzhiyun ldr r4, =ESDCTL_DDR2_RESET_DLL 191*4882a593Smuzhiyun strb r3, [r1, r4] 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun ldr r3, =ESDCTL_0x92220000 194*4882a593Smuzhiyun strlo r3, [r0, #0x0] 195*4882a593Smuzhiyun strhs r3, [r0, #0x8] 196*4882a593Smuzhiyun mov r3, #0xDA 197*4882a593Smuzhiyun ldr r4, =ESDCTL_PRECHARGE 198*4882a593Smuzhiyun strb r3, [r1, r4] 199*4882a593Smuzhiyun 200*4882a593Smuzhiyunskip_set_mode: 201*4882a593Smuzhiyun cmp r1, #CSD1_BASE_ADDR 202*4882a593Smuzhiyun ldr r3, =ESDCTL_0xA2220000 203*4882a593Smuzhiyun strlo r3, [r0, #0x0] 204*4882a593Smuzhiyun strhs r3, [r0, #0x8] 205*4882a593Smuzhiyun mov r3, #0xDA 206*4882a593Smuzhiyun strb r3, [r1] 207*4882a593Smuzhiyun strb r3, [r1] 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun ldr r3, =ESDCTL_0xB2220000 210*4882a593Smuzhiyun strlo r3, [r0, #0x0] 211*4882a593Smuzhiyun strhs r3, [r0, #0x8] 212*4882a593Smuzhiyun tst r2, #0x1 213*4882a593Smuzhiyun ldreq r4, =ESDCTL_DDR2_MR 214*4882a593Smuzhiyun ldrne r4, =ESDCTL_MDDR_MR 215*4882a593Smuzhiyun mov r3, #0xDA 216*4882a593Smuzhiyun strb r3, [r1, r4] 217*4882a593Smuzhiyun ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT 218*4882a593Smuzhiyun streqb r3, [r1, r4] 219*4882a593Smuzhiyun ldreq r4, =ESDCTL_DDR2_EN_DLL 220*4882a593Smuzhiyun ldrne r4, =ESDCTL_MDDR_EMR 221*4882a593Smuzhiyun strb r3, [r1, r4] 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun cmp r1, #CSD1_BASE_ADDR 224*4882a593Smuzhiyun ldr r3, =ESDCTL_0x82228080 225*4882a593Smuzhiyun strlo r3, [r0, #0x0] 226*4882a593Smuzhiyun strhs r3, [r0, #0x8] 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun tst r2, #0x1 229*4882a593Smuzhiyun moveq r4, #0x20000 230*4882a593Smuzhiyun movne r4, #0x200 231*4882a593Smuzhiyun1: subs r4, r4, #1 232*4882a593Smuzhiyun bne 1b 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun str r3, [r1, #0x100] 235*4882a593Smuzhiyun ldr r4, [r1, #0x100] 236*4882a593Smuzhiyun cmp r3, r4 237*4882a593Smuzhiyun movne r3, #1 238*4882a593Smuzhiyun moveq r3, #0 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun mov pc, lr 241