1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include <config.h> 8*4882a593Smuzhiyun#include <asm/arch/imx-regs.h> 9*4882a593Smuzhiyun#include <asm/macro.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun.globl lowlevel_init 12*4882a593Smuzhiyunlowlevel_init: 13*4882a593Smuzhiyun /* Also setup the Peripheral Port Remap register inside the core */ 14*4882a593Smuzhiyun ldr r0, =ARM_PPMRR /* start from AIPS 2GB region */ 15*4882a593Smuzhiyun mcr p15, 0, r0, c15, c2, 4 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun write32 IPU_CONF, IPU_CONF_DI_EN 18*4882a593Smuzhiyun write32 CCM_CCMR, CCM_CCMR_SETUP 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun wait_timer 0x40000 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun write32 CCM_CCMR, CCM_CCMR_SETUP | CCMR_MPE 23*4882a593Smuzhiyun write32 CCM_CCMR, (CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Set up clock to 532MHz */ 26*4882a593Smuzhiyun write32 CCM_PDR0, CCM_PDR0_SETUP_532MHZ 27*4882a593Smuzhiyun write32 CCM_MPCTL, CCM_MPCTL_SETUP_532MHZ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun write32 CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* Set up MX31 DDR pins */ 32*4882a593Smuzhiyun write32 IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B, 0 33*4882a593Smuzhiyun write32 IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0, 0 34*4882a593Smuzhiyun write32 IOMUXC_SW_PAD_CTL_BCLK_RW_RAS, 0 35*4882a593Smuzhiyun write32 IOMUXC_SW_PAD_CTL_CS2_CS3_CS4, 0x1000 36*4882a593Smuzhiyun write32 IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1, 0 37*4882a593Smuzhiyun write32 IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2, 0 38*4882a593Smuzhiyun write32 IOMUXC_SW_PAD_CTL_SD29_SD30_SD31, 0 39*4882a593Smuzhiyun write32 IOMUXC_SW_PAD_CTL_SD26_SD27_SD28, 0 40*4882a593Smuzhiyun write32 IOMUXC_SW_PAD_CTL_SD23_SD24_SD25, 0 41*4882a593Smuzhiyun write32 IOMUXC_SW_PAD_CTL_SD20_SD21_SD22, 0 42*4882a593Smuzhiyun write32 IOMUXC_SW_PAD_CTL_SD17_SD18_SD19, 0 43*4882a593Smuzhiyun write32 IOMUXC_SW_PAD_CTL_SD14_SD15_SD16, 0 44*4882a593Smuzhiyun write32 IOMUXC_SW_PAD_CTL_SD11_SD12_SD13, 0 45*4882a593Smuzhiyun write32 IOMUXC_SW_PAD_CTL_SD8_SD9_SD10, 0 46*4882a593Smuzhiyun write32 IOMUXC_SW_PAD_CTL_SD5_SD6_SD7, 0 47*4882a593Smuzhiyun write32 IOMUXC_SW_PAD_CTL_SD2_SD3_SD4, 0 48*4882a593Smuzhiyun write32 IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1, 0 49*4882a593Smuzhiyun write32 IOMUXC_SW_PAD_CTL_A24_A25_SDBA1, 0 50*4882a593Smuzhiyun write32 IOMUXC_SW_PAD_CTL_A21_A22_A23, 0 51*4882a593Smuzhiyun write32 IOMUXC_SW_PAD_CTL_A18_A19_A20, 0 52*4882a593Smuzhiyun write32 IOMUXC_SW_PAD_CTL_A15_A16_A17, 0 53*4882a593Smuzhiyun write32 IOMUXC_SW_PAD_CTL_A12_A13_A14, 0 54*4882a593Smuzhiyun write32 IOMUXC_SW_PAD_CTL_A10_MA10_A11, 0 55*4882a593Smuzhiyun write32 IOMUXC_SW_PAD_CTL_A7_A8_A9, 0 56*4882a593Smuzhiyun write32 IOMUXC_SW_PAD_CTL_A4_A5_A6, 0 57*4882a593Smuzhiyun write32 IOMUXC_SW_PAD_CTL_A1_A2_A3, 0 58*4882a593Smuzhiyun write32 IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0, 0 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* Set up MX31 DDR Memory Controller */ 61*4882a593Smuzhiyun write32 WEIM_ESDMISC, ESDMISC_MDDR_SETUP 62*4882a593Smuzhiyun write32 WEIM_ESDCFG0, ESDCFG0_MDDR_SETUP 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* Perform DDR init sequence */ 65*4882a593Smuzhiyun write32 WEIM_ESDCTL0, ESDCTL_PRECHARGE 66*4882a593Smuzhiyun write32 CSD0_BASE | 0x0f00, 0x12344321 67*4882a593Smuzhiyun write32 WEIM_ESDCTL0, ESDCTL_AUTOREFRESH 68*4882a593Smuzhiyun write32 CSD0_BASE, 0x12344321 69*4882a593Smuzhiyun write32 CSD0_BASE, 0x12344321 70*4882a593Smuzhiyun write32 WEIM_ESDCTL0, ESDCTL_LOADMODEREG 71*4882a593Smuzhiyun write8 CSD0_BASE | 0x00000033, 0xda 72*4882a593Smuzhiyun write8 CSD0_BASE | 0x01000000, 0xff 73*4882a593Smuzhiyun write32 WEIM_ESDCTL0, ESDCTL_RW 74*4882a593Smuzhiyun write32 CSD0_BASE, 0xDEADBEEF 75*4882a593Smuzhiyun write32 WEIM_ESDMISC, ESDMISC_MDDR_RESET_DL 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun mov pc, lr 78