1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <netdev.h>
9*4882a593Smuzhiyun #include <asm/io.h>
10*4882a593Smuzhiyun #include <asm/arch/clock.h>
11*4882a593Smuzhiyun #include <asm/arch/imx-regs.h>
12*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
15*4882a593Smuzhiyun
dram_init(void)16*4882a593Smuzhiyun int dram_init(void)
17*4882a593Smuzhiyun {
18*4882a593Smuzhiyun /* dram_init must store complete ramsize in gd->ram_size */
19*4882a593Smuzhiyun gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
20*4882a593Smuzhiyun PHYS_SDRAM_1_SIZE);
21*4882a593Smuzhiyun return 0;
22*4882a593Smuzhiyun }
23*4882a593Smuzhiyun
board_early_init_f(void)24*4882a593Smuzhiyun int board_early_init_f(void)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun int i;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* CS0: Nor Flash */
29*4882a593Smuzhiyun /*
30*4882a593Smuzhiyun * CS0L and CS0A values are from the RedBoot sources by Freescale
31*4882a593Smuzhiyun * and are also equal to those used by Sascha Hauer for the Phytec
32*4882a593Smuzhiyun * i.MX31 board. CS0U is just a slightly optimized hardware default:
33*4882a593Smuzhiyun * the only non-zero field "Wait State Control" is set to half the
34*4882a593Smuzhiyun * default value.
35*4882a593Smuzhiyun */
36*4882a593Smuzhiyun static const struct mxc_weimcs cs0 = {
37*4882a593Smuzhiyun /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
38*4882a593Smuzhiyun CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0),
39*4882a593Smuzhiyun /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
40*4882a593Smuzhiyun CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1),
41*4882a593Smuzhiyun /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
42*4882a593Smuzhiyun CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0)
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun mxc_setup_weimcs(0, &cs0);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /* setup pins for UART1 */
48*4882a593Smuzhiyun mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
49*4882a593Smuzhiyun mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
50*4882a593Smuzhiyun mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
51*4882a593Smuzhiyun mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* SPI2 */
54*4882a593Smuzhiyun mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
55*4882a593Smuzhiyun mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
56*4882a593Smuzhiyun mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
57*4882a593Smuzhiyun mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
58*4882a593Smuzhiyun mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
59*4882a593Smuzhiyun mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
60*4882a593Smuzhiyun mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /* start SPI2 clock */
63*4882a593Smuzhiyun __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* PBC setup */
66*4882a593Smuzhiyun /* Enable UART transceivers also reset the Ethernet/external UART */
67*4882a593Smuzhiyun readw(CS4_BASE + 4);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun writew(0x8023, CS4_BASE + 4);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun /* RedBoot also has an empty loop with 100000 iterations here -
72*4882a593Smuzhiyun * clock doesn't run yet */
73*4882a593Smuzhiyun for (i = 0; i < 100000; i++)
74*4882a593Smuzhiyun ;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /* Clear the reset, toggle the LEDs */
77*4882a593Smuzhiyun writew(0xDF, CS4_BASE + 6);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun /* clock still doesn't run */
80*4882a593Smuzhiyun for (i = 0; i < 100000; i++)
81*4882a593Smuzhiyun ;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /* See 1.5.4 in IMX31ADSE_PERI_BUS_CNTRL_CPLD_RM.pdf */
84*4882a593Smuzhiyun readb(CS4_BASE + 8);
85*4882a593Smuzhiyun readb(CS4_BASE + 7);
86*4882a593Smuzhiyun readb(CS4_BASE + 8);
87*4882a593Smuzhiyun readb(CS4_BASE + 7);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun return 0;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
board_init(void)92*4882a593Smuzhiyun int board_init(void)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun gd->bd->bi_boot_params = 0x80000100; /* adress of boot parameters */
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun return 0;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
checkboard(void)99*4882a593Smuzhiyun int checkboard(void)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun printf("Board: MX31ADS\n");
102*4882a593Smuzhiyun return 0;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun #ifdef CONFIG_CMD_NET
board_eth_init(bd_t * bis)106*4882a593Smuzhiyun int board_eth_init(bd_t *bis)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun int rc = 0;
109*4882a593Smuzhiyun #ifdef CONFIG_CS8900
110*4882a593Smuzhiyun rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
111*4882a593Smuzhiyun #endif
112*4882a593Smuzhiyun return rc;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun #endif
115