1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Freescale MX28EVK board
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * (C) Copyright 2011 Freescale Semiconductor, Inc.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Author: Fabio Estevam <fabio.estevam@freescale.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Based on m28evk.c:
9*4882a593Smuzhiyun * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
10*4882a593Smuzhiyun * on behalf of DENX Software Engineering GmbH
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <common.h>
16*4882a593Smuzhiyun #include <asm/gpio.h>
17*4882a593Smuzhiyun #include <asm/io.h>
18*4882a593Smuzhiyun #include <asm/arch/imx-regs.h>
19*4882a593Smuzhiyun #include <asm/arch/iomux-mx28.h>
20*4882a593Smuzhiyun #include <asm/arch/clock.h>
21*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
22*4882a593Smuzhiyun #include <linux/mii.h>
23*4882a593Smuzhiyun #include <miiphy.h>
24*4882a593Smuzhiyun #include <netdev.h>
25*4882a593Smuzhiyun #include <errno.h>
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /*
30*4882a593Smuzhiyun * Functions
31*4882a593Smuzhiyun */
board_early_init_f(void)32*4882a593Smuzhiyun int board_early_init_f(void)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun /* IO0 clock at 480MHz */
35*4882a593Smuzhiyun mxs_set_ioclk(MXC_IOCLK0, 480000);
36*4882a593Smuzhiyun /* IO1 clock at 480MHz */
37*4882a593Smuzhiyun mxs_set_ioclk(MXC_IOCLK1, 480000);
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* SSP0 clock at 96MHz */
40*4882a593Smuzhiyun mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
41*4882a593Smuzhiyun /* SSP2 clock at 160MHz */
42*4882a593Smuzhiyun mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #ifdef CONFIG_CMD_USB
45*4882a593Smuzhiyun mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
46*4882a593Smuzhiyun mxs_iomux_setup_pad(MX28_PAD_AUART2_RX__GPIO_3_8 |
47*4882a593Smuzhiyun MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL);
48*4882a593Smuzhiyun gpio_direction_output(MX28_PAD_AUART2_RX__GPIO_3_8, 1);
49*4882a593Smuzhiyun #endif
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /* Power on LCD */
52*4882a593Smuzhiyun gpio_direction_output(MX28_PAD_LCD_RESET__GPIO_3_30, 1);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /* Set contrast to maximum */
55*4882a593Smuzhiyun gpio_direction_output(MX28_PAD_PWM2__GPIO_3_18, 1);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun return 0;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
dram_init(void)60*4882a593Smuzhiyun int dram_init(void)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun return mxs_dram_init();
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
board_init(void)65*4882a593Smuzhiyun int board_init(void)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun /* Adress of boot parameters */
68*4882a593Smuzhiyun gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun return 0;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun #ifdef CONFIG_CMD_MMC
mx28evk_mmc_wp(int id)74*4882a593Smuzhiyun static int mx28evk_mmc_wp(int id)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun if (id != 0) {
77*4882a593Smuzhiyun printf("MXS MMC: Invalid card selected (card id = %d)\n", id);
78*4882a593Smuzhiyun return 1;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun return gpio_get_value(MX28_PAD_SSP1_SCK__GPIO_2_12);
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
board_mmc_init(bd_t * bis)84*4882a593Smuzhiyun int board_mmc_init(bd_t *bis)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun /* Configure WP as input */
87*4882a593Smuzhiyun gpio_direction_input(MX28_PAD_SSP1_SCK__GPIO_2_12);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /* Configure MMC0 Power Enable */
90*4882a593Smuzhiyun gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun return mxsmmc_initialize(bis, 0, mx28evk_mmc_wp, NULL);
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun #endif
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun #ifdef CONFIG_CMD_NET
97*4882a593Smuzhiyun
board_eth_init(bd_t * bis)98*4882a593Smuzhiyun int board_eth_init(bd_t *bis)
99*4882a593Smuzhiyun {
100*4882a593Smuzhiyun struct mxs_clkctrl_regs *clkctrl_regs =
101*4882a593Smuzhiyun (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
102*4882a593Smuzhiyun struct eth_device *dev;
103*4882a593Smuzhiyun int ret;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun ret = cpu_eth_init(bis);
106*4882a593Smuzhiyun if (ret)
107*4882a593Smuzhiyun return ret;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* MX28EVK uses ENET_CLK PAD to drive FEC clock */
110*4882a593Smuzhiyun writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN,
111*4882a593Smuzhiyun &clkctrl_regs->hw_clkctrl_enet);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun /* Power-on FECs */
114*4882a593Smuzhiyun gpio_direction_output(MX28_PAD_SSP1_DATA3__GPIO_2_15, 0);
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun /* Reset FEC PHYs */
117*4882a593Smuzhiyun gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
118*4882a593Smuzhiyun udelay(200);
119*4882a593Smuzhiyun gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
122*4882a593Smuzhiyun if (ret) {
123*4882a593Smuzhiyun puts("FEC MXS: Unable to init FEC0\n");
124*4882a593Smuzhiyun return ret;
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
128*4882a593Smuzhiyun if (ret) {
129*4882a593Smuzhiyun puts("FEC MXS: Unable to init FEC1\n");
130*4882a593Smuzhiyun return ret;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun dev = eth_get_dev_by_name("FEC0");
134*4882a593Smuzhiyun if (!dev) {
135*4882a593Smuzhiyun puts("FEC MXS: Unable to get FEC0 device entry\n");
136*4882a593Smuzhiyun return -EINVAL;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun dev = eth_get_dev_by_name("FEC1");
140*4882a593Smuzhiyun if (!dev) {
141*4882a593Smuzhiyun puts("FEC MXS: Unable to get FEC1 device entry\n");
142*4882a593Smuzhiyun return -EINVAL;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun return ret;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun #endif
149