xref: /OK3568_Linux_fs/u-boot/board/freescale/mx25pdk/mx25pdk.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * (C) Copyright 2011 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Author: Fabio Estevam <fabio.estevam@freescale.com>
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun #include <asm/gpio.h>
12*4882a593Smuzhiyun #include <asm/arch/imx-regs.h>
13*4882a593Smuzhiyun #include <asm/arch/iomux-mx25.h>
14*4882a593Smuzhiyun #include <asm/arch/clock.h>
15*4882a593Smuzhiyun #include <mmc.h>
16*4882a593Smuzhiyun #include <fsl_esdhc.h>
17*4882a593Smuzhiyun #include <i2c.h>
18*4882a593Smuzhiyun #include <power/pmic.h>
19*4882a593Smuzhiyun #include <fsl_pmic.h>
20*4882a593Smuzhiyun #include <mc34704.h>
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #define FEC_RESET_B		IMX_GPIO_NR(4, 8)
23*4882a593Smuzhiyun #define FEC_ENABLE_B		IMX_GPIO_NR(2, 3)
24*4882a593Smuzhiyun #define CARD_DETECT		IMX_GPIO_NR(2, 1)
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #ifdef CONFIG_FSL_ESDHC
29*4882a593Smuzhiyun struct fsl_esdhc_cfg esdhc_cfg[1] = {
30*4882a593Smuzhiyun 	{IMX_MMC_SDHC1_BASE},
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun #endif
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun /*
35*4882a593Smuzhiyun  * FIXME: need to revisit this
36*4882a593Smuzhiyun  * The original code enabled PUE and 100-k pull-down without PKE, so the right
37*4882a593Smuzhiyun  * value here is likely:
38*4882a593Smuzhiyun  *	0 for no pull
39*4882a593Smuzhiyun  * or:
40*4882a593Smuzhiyun  *	PAD_CTL_PUS_100K_DOWN for 100-k pull-down
41*4882a593Smuzhiyun  */
42*4882a593Smuzhiyun #define FEC_OUT_PAD_CTRL	0
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun #define I2C_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
45*4882a593Smuzhiyun 				 PAD_CTL_ODE)
46*4882a593Smuzhiyun 
mx25pdk_fec_init(void)47*4882a593Smuzhiyun static void mx25pdk_fec_init(void)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun 	static const iomux_v3_cfg_t fec_pads[] = {
50*4882a593Smuzhiyun 		MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
51*4882a593Smuzhiyun 		MX25_PAD_FEC_RX_DV__FEC_RX_DV,
52*4882a593Smuzhiyun 		MX25_PAD_FEC_RDATA0__FEC_RDATA0,
53*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL),
54*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL),
55*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL),
56*4882a593Smuzhiyun 		MX25_PAD_FEC_MDIO__FEC_MDIO,
57*4882a593Smuzhiyun 		MX25_PAD_FEC_RDATA1__FEC_RDATA1,
58*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL),
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_D12__GPIO_4_8, 0), /* FEC_RESET_B */
61*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_A17__GPIO_2_3, 0), /* FEC_ENABLE_B */
62*4882a593Smuzhiyun 	};
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun 	static const iomux_v3_cfg_t i2c_pads[] = {
65*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_I2C1_CLK__I2C1_CLK, I2C_PAD_CTRL),
66*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_I2C1_DAT__I2C1_DAT, I2C_PAD_CTRL),
67*4882a593Smuzhiyun 	};
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 	/* Assert RESET and ENABLE low */
72*4882a593Smuzhiyun 	gpio_direction_output(FEC_RESET_B, 0);
73*4882a593Smuzhiyun 	gpio_direction_output(FEC_ENABLE_B, 0);
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun 	udelay(10);
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 	/* Deassert RESET and ENABLE */
78*4882a593Smuzhiyun 	gpio_set_value(FEC_RESET_B, 1);
79*4882a593Smuzhiyun 	gpio_set_value(FEC_ENABLE_B, 1);
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun 	/* Setup I2C pins so that PMIC can turn on PHY supply */
82*4882a593Smuzhiyun 	imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun 
dram_init(void)85*4882a593Smuzhiyun int dram_init(void)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun 	/* dram_init must store complete ramsize in gd->ram_size */
88*4882a593Smuzhiyun 	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
89*4882a593Smuzhiyun 				PHYS_SDRAM_1_SIZE);
90*4882a593Smuzhiyun 	return 0;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun /*
94*4882a593Smuzhiyun  * Set up input pins with hysteresis and 100-k pull-ups
95*4882a593Smuzhiyun  */
96*4882a593Smuzhiyun #define UART1_IN_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PUS_100K_UP)
97*4882a593Smuzhiyun /*
98*4882a593Smuzhiyun  * FIXME: need to revisit this
99*4882a593Smuzhiyun  * The original code enabled PUE and 100-k pull-down without PKE, so the right
100*4882a593Smuzhiyun  * value here is likely:
101*4882a593Smuzhiyun  *	0 for no pull
102*4882a593Smuzhiyun  * or:
103*4882a593Smuzhiyun  *	PAD_CTL_PUS_100K_DOWN for 100-k pull-down
104*4882a593Smuzhiyun  */
105*4882a593Smuzhiyun #define UART1_OUT_PAD_CTRL	0
106*4882a593Smuzhiyun 
mx25pdk_uart1_init(void)107*4882a593Smuzhiyun static void mx25pdk_uart1_init(void)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun 	static const iomux_v3_cfg_t uart1_pads[] = {
110*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_UART1_RXD__UART1_RXD, UART1_IN_PAD_CTRL),
111*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_UART1_TXD__UART1_TXD, UART1_OUT_PAD_CTRL),
112*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_UART1_RTS__UART1_RTS, UART1_OUT_PAD_CTRL),
113*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_UART1_CTS__UART1_CTS, UART1_IN_PAD_CTRL),
114*4882a593Smuzhiyun 	};
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun 
board_early_init_f(void)119*4882a593Smuzhiyun int board_early_init_f(void)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun 	mx25pdk_uart1_init();
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	return 0;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun 
board_init(void)126*4882a593Smuzhiyun int board_init(void)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun 	/* address of boot parameters */
129*4882a593Smuzhiyun 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 	return 0;
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun 
board_late_init(void)134*4882a593Smuzhiyun int board_late_init(void)
135*4882a593Smuzhiyun {
136*4882a593Smuzhiyun 	struct pmic *p;
137*4882a593Smuzhiyun 	int ret;
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	mx25pdk_fec_init();
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	ret = pmic_init(I2C_0);
142*4882a593Smuzhiyun 	if (ret)
143*4882a593Smuzhiyun 		return ret;
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	p = pmic_get("FSL_PMIC");
146*4882a593Smuzhiyun 	if (!p)
147*4882a593Smuzhiyun 		return -ENODEV;
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	/* Turn on Ethernet PHY and LCD supplies */
150*4882a593Smuzhiyun 	pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE | ONOFFA);
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	return 0;
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun #ifdef CONFIG_FSL_ESDHC
board_mmc_getcd(struct mmc * mmc)156*4882a593Smuzhiyun int board_mmc_getcd(struct mmc *mmc)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun 	/* Set up the Card Detect pin. */
159*4882a593Smuzhiyun 	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX25_PAD_A15__GPIO_2_1, 0));
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	gpio_direction_input(CARD_DETECT);
162*4882a593Smuzhiyun 	return !gpio_get_value(CARD_DETECT);
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun 
board_mmc_init(bd_t * bis)165*4882a593Smuzhiyun int board_mmc_init(bd_t *bis)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun 	static const iomux_v3_cfg_t sdhc1_pads[] = {
168*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_SD1_CMD__SD1_CMD, NO_PAD_CTRL),
169*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_SD1_CLK__SD1_CLK, NO_PAD_CTRL),
170*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_SD1_DATA0__SD1_DATA0, NO_PAD_CTRL),
171*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_SD1_DATA1__SD1_DATA1, NO_PAD_CTRL),
172*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_SD1_DATA2__SD1_DATA2, NO_PAD_CTRL),
173*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_SD1_DATA3__SD1_DATA3, NO_PAD_CTRL),
174*4882a593Smuzhiyun 	};
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun 	imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	/*
179*4882a593Smuzhiyun 	 * Set the eSDHC1 PER clock to the maximum frequency lower than or equal
180*4882a593Smuzhiyun 	 * to 50 MHz that can be obtained, which requires to use UPLL as the
181*4882a593Smuzhiyun 	 * clock source. This actually gives 48 MHz.
182*4882a593Smuzhiyun 	 */
183*4882a593Smuzhiyun 	imx_set_perclk(MXC_ESDHC1_CLK, true, 50000000);
184*4882a593Smuzhiyun 	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
185*4882a593Smuzhiyun 	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun #endif
188*4882a593Smuzhiyun 
checkboard(void)189*4882a593Smuzhiyun int checkboard(void)
190*4882a593Smuzhiyun {
191*4882a593Smuzhiyun 	puts("Board: MX25PDK\n");
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	return 0;
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun /* Lowlevel init isn't used on mx25pdk, so just provide a dummy one here */
lowlevel_init(void)197*4882a593Smuzhiyun void lowlevel_init(void) {}
198