1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2008,2011 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <fsl_ddr_sdram.h>
10*4882a593Smuzhiyun #include <fsl_ddr_dimm_params.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun struct board_specific_parameters {
13*4882a593Smuzhiyun u32 n_ranks;
14*4882a593Smuzhiyun u32 datarate_mhz_high;
15*4882a593Smuzhiyun u32 clk_adjust;
16*4882a593Smuzhiyun u32 cpo;
17*4882a593Smuzhiyun u32 write_data_delay;
18*4882a593Smuzhiyun };
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /*
21*4882a593Smuzhiyun * This table contains all valid speeds we want to override with board
22*4882a593Smuzhiyun * specific parameters. datarate_mhz_high values need to be in ascending order
23*4882a593Smuzhiyun * for each n_ranks group.
24*4882a593Smuzhiyun */
25*4882a593Smuzhiyun const struct board_specific_parameters dimm0[] = {
26*4882a593Smuzhiyun /*
27*4882a593Smuzhiyun * memory controller 0
28*4882a593Smuzhiyun * num| hi| clk| cpo|wrdata|2T
29*4882a593Smuzhiyun * ranks| mhz|adjst| | delay|
30*4882a593Smuzhiyun */
31*4882a593Smuzhiyun {4, 333, 7, 7, 3},
32*4882a593Smuzhiyun {4, 549, 7, 9, 3},
33*4882a593Smuzhiyun {4, 650, 7, 10, 4},
34*4882a593Smuzhiyun {2, 333, 7, 7, 3},
35*4882a593Smuzhiyun {2, 549, 7, 9, 3},
36*4882a593Smuzhiyun {2, 650, 7, 10, 4},
37*4882a593Smuzhiyun {1, 333, 7, 7, 3},
38*4882a593Smuzhiyun {1, 549, 7, 9, 3},
39*4882a593Smuzhiyun {1, 650, 7, 10, 4},
40*4882a593Smuzhiyun {}
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /*
44*4882a593Smuzhiyun * The two slots have slightly different timing. The center values are good
45*4882a593Smuzhiyun * for both slots. We use identical speed tables for them. In future use, if
46*4882a593Smuzhiyun * DIMMs have fewer center values that require two separated tables, copy the
47*4882a593Smuzhiyun * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
48*4882a593Smuzhiyun */
49*4882a593Smuzhiyun const struct board_specific_parameters *dimms[] = {
50*4882a593Smuzhiyun dimm0,
51*4882a593Smuzhiyun dimm0,
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)54*4882a593Smuzhiyun void fsl_ddr_board_options(memctl_options_t *popts,
55*4882a593Smuzhiyun dimm_params_t *pdimm,
56*4882a593Smuzhiyun unsigned int ctrl_num)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
59*4882a593Smuzhiyun unsigned int i;
60*4882a593Smuzhiyun ulong ddr_freq;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun if (ctrl_num > 1) {
63*4882a593Smuzhiyun printf("Wrong parameter for controller number %d", ctrl_num);
64*4882a593Smuzhiyun return;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
67*4882a593Smuzhiyun if (pdimm[i].n_ranks)
68*4882a593Smuzhiyun break;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */
71*4882a593Smuzhiyun return;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun pbsp = dimms[ctrl_num];
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* Get clk_adjust, cpo, write_data_delay, according to the board ddr
76*4882a593Smuzhiyun * freqency and n_banks specified in board_specific_parameters table.
77*4882a593Smuzhiyun */
78*4882a593Smuzhiyun ddr_freq = get_ddr_freq(0) / 1000000;
79*4882a593Smuzhiyun while (pbsp->datarate_mhz_high) {
80*4882a593Smuzhiyun if (pbsp->n_ranks == pdimm[i].n_ranks) {
81*4882a593Smuzhiyun if (ddr_freq <= pbsp->datarate_mhz_high) {
82*4882a593Smuzhiyun popts->clk_adjust = pbsp->clk_adjust;
83*4882a593Smuzhiyun popts->cpo_override = pbsp->cpo;
84*4882a593Smuzhiyun popts->write_data_delay =
85*4882a593Smuzhiyun pbsp->write_data_delay;
86*4882a593Smuzhiyun goto found;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun pbsp_highest = pbsp;
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun pbsp++;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun if (pbsp_highest) {
94*4882a593Smuzhiyun printf("Error: board specific timing not found "
95*4882a593Smuzhiyun "for data rate %lu MT/s!\n"
96*4882a593Smuzhiyun "Trying to use the highest speed (%u) parameters\n",
97*4882a593Smuzhiyun ddr_freq, pbsp_highest->datarate_mhz_high);
98*4882a593Smuzhiyun popts->clk_adjust = pbsp_highest->clk_adjust;
99*4882a593Smuzhiyun popts->cpo_override = pbsp_highest->cpo;
100*4882a593Smuzhiyun popts->write_data_delay = pbsp_highest->write_data_delay;
101*4882a593Smuzhiyun } else {
102*4882a593Smuzhiyun panic("DIMM is not supported by this board");
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun found:
106*4882a593Smuzhiyun /* 2T timing enable */
107*4882a593Smuzhiyun popts->twot_en = 1;
108*4882a593Smuzhiyun }
109