1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2009-2010 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2000 5*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <common.h> 11*4882a593Smuzhiyun #include <asm/mmu.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct fsl_e_tlb_entry tlb_table[] = { 14*4882a593Smuzhiyun /* TLB 0 - for temp stack in cache */ 15*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 16*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 17*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 18*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 19*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 20*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 21*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 22*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 23*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 24*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 25*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 26*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 27*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 28*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 29*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* TLB 1 Initializations */ 32*4882a593Smuzhiyun /* 33*4882a593Smuzhiyun * TLBe 0: 64M write-through, guarded 34*4882a593Smuzhiyun * Out of reset this entry is only 4K. 35*4882a593Smuzhiyun * 0xfc000000 32MB NAND FLASH (CS3) 36*4882a593Smuzhiyun * 0xfe000000 32MB NOR FLASH (CS0) 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun #ifdef CONFIG_NAND_SPL 39*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE, 40*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 41*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_1M, 1), 42*4882a593Smuzhiyun #else 43*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE, 44*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, 45*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_64M, 1), 46*4882a593Smuzhiyun #endif 47*4882a593Smuzhiyun /* 48*4882a593Smuzhiyun * TLBe 1: 256KB Non-cacheable, guarded 49*4882a593Smuzhiyun * 0xf8000000 32K BCSR 50*4882a593Smuzhiyun * 0xf8008000 32K PIB (CS4) 51*4882a593Smuzhiyun * 0xf8010000 32K PIB (CS5) 52*4882a593Smuzhiyun */ 53*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS, 54*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 55*4882a593Smuzhiyun 0, 1, BOOKE_PAGESZ_256K, 1), 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* 58*4882a593Smuzhiyun * TLBe 2: 256M Non-cacheable, guarded 59*4882a593Smuzhiyun * 0xa00000000 256M PCIe MEM (lower half) 60*4882a593Smuzhiyun */ 61*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 62*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 63*4882a593Smuzhiyun 0, 2, BOOKE_PAGESZ_256M, 1), 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* 66*4882a593Smuzhiyun * TLBe 3: 256M Non-cacheable, guarded 67*4882a593Smuzhiyun * 0xb00000000 256M PCIe MEM (higher half) 68*4882a593Smuzhiyun */ 69*4882a593Smuzhiyun SET_TLB_ENTRY(1, (CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000), 70*4882a593Smuzhiyun (CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000), 71*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 72*4882a593Smuzhiyun 0, 3, BOOKE_PAGESZ_256M, 1), 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* 75*4882a593Smuzhiyun * TLBe 4: 64M Non-cacheable, guarded 76*4882a593Smuzhiyun * 0xe000_0000 1M CCSRBAR 77*4882a593Smuzhiyun * 0xe280_0000 8M PCIe IO 78*4882a593Smuzhiyun */ 79*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 80*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 81*4882a593Smuzhiyun 0, 4, BOOKE_PAGESZ_64M, 1), 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 84*4882a593Smuzhiyun /* *I*G - L2SRAM */ 85*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, 86*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 87*4882a593Smuzhiyun 0, 5, BOOKE_PAGESZ_256K, 1), 88*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, 89*4882a593Smuzhiyun CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, 90*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 91*4882a593Smuzhiyun 0, 6, BOOKE_PAGESZ_256K, 1), 92*4882a593Smuzhiyun #endif 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun int num_tlb_entries = ARRAY_SIZE(tlb_table); 96