1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2009-2011 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2000 5*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <common.h> 11*4882a593Smuzhiyun #include <asm/fsl_law.h> 12*4882a593Smuzhiyun #include <asm/mmu.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * LAW(Local Access Window) configuration: 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun *0) 0x0000_0000 0x7fff_ffff DDR 2G 18*4882a593Smuzhiyun *1) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB 19*4882a593Smuzhiyun *-) 0xe000_0000 0xe00f_ffff CCSR 1M 20*4882a593Smuzhiyun *2) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M 21*4882a593Smuzhiyun *3) 0xc000_0000 0xdfff_ffff SRIO 512MB 22*4882a593Smuzhiyun *4.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB 23*4882a593Smuzhiyun *4.b) 0xf800_0000 0xf800_7fff BCSR 32KB 24*4882a593Smuzhiyun *4.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB 25*4882a593Smuzhiyun *4.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB 26*4882a593Smuzhiyun *4.e) 0xfe00_0000 0xffff_ffff Flash 32MB 27*4882a593Smuzhiyun * 28*4882a593Smuzhiyun *Notes: 29*4882a593Smuzhiyun * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. 30*4882a593Smuzhiyun * If flash is 8M at default position (last 8M), no LAW needed. 31*4882a593Smuzhiyun * 32*4882a593Smuzhiyun */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun struct law_entry law_table[] = { 35*4882a593Smuzhiyun #ifndef CONFIG_SPD_EEPROM 36*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_1G, LAW_TRGT_IF_DDR), 37*4882a593Smuzhiyun #endif 38*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC), 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun int num_law_entries = ARRAY_SIZE(law_table); 42