1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2009 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <common.h> 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <fsl_ddr_sdram.h> 10*4882a593Smuzhiyun #include <fsl_ddr_dimm_params.h> 11*4882a593Smuzhiyun fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)12*4882a593Smuzhiyunvoid fsl_ddr_board_options(memctl_options_t *popts, 13*4882a593Smuzhiyun dimm_params_t *pdimm, 14*4882a593Smuzhiyun unsigned int ctrl_num) 15*4882a593Smuzhiyun { 16*4882a593Smuzhiyun /* 17*4882a593Smuzhiyun * Factors to consider for clock adjust: 18*4882a593Smuzhiyun * - number of chips on bus 19*4882a593Smuzhiyun * - position of slot 20*4882a593Smuzhiyun * - DDR1 vs. DDR2? 21*4882a593Smuzhiyun * - ??? 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * This needs to be determined on a board-by-board basis. 24*4882a593Smuzhiyun * 0110 3/4 cycle late 25*4882a593Smuzhiyun * 0111 7/8 cycle late 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun popts->clk_adjust = 4; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* 30*4882a593Smuzhiyun * Factors to consider for CPO: 31*4882a593Smuzhiyun * - frequency 32*4882a593Smuzhiyun * - ddr1 vs. ddr2 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun popts->cpo_override = 0xff; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* 37*4882a593Smuzhiyun * Factors to consider for write data delay: 38*4882a593Smuzhiyun * - number of DIMMs 39*4882a593Smuzhiyun * 40*4882a593Smuzhiyun * 1 = 1/4 clock delay 41*4882a593Smuzhiyun * 2 = 1/2 clock delay 42*4882a593Smuzhiyun * 3 = 3/4 clock delay 43*4882a593Smuzhiyun * 4 = 1 clock delay 44*4882a593Smuzhiyun * 5 = 5/4 clock delay 45*4882a593Smuzhiyun * 6 = 3/2 clock delay 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun popts->write_data_delay = 2; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* 50*4882a593Smuzhiyun * Enable half drive strength 51*4882a593Smuzhiyun */ 52*4882a593Smuzhiyun popts->half_strength_driver_enable = 1; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* Write leveling override */ 55*4882a593Smuzhiyun popts->wrlvl_en = 1; 56*4882a593Smuzhiyun popts->wrlvl_override = 1; 57*4882a593Smuzhiyun popts->wrlvl_sample = 0xa; 58*4882a593Smuzhiyun popts->wrlvl_start = 0x4; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* Rtt and Rtt_W override */ 61*4882a593Smuzhiyun popts->rtt_override = 1; 62*4882a593Smuzhiyun popts->rtt_override_value = DDR3_RTT_60_OHM; 63*4882a593Smuzhiyun popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */ 64*4882a593Smuzhiyun } 65