1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2009 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __BCSR_H_ 8*4882a593Smuzhiyun #define __BCSR_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <common.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* BCSR Bit definitions*/ 13*4882a593Smuzhiyun /****************************************/ 14*4882a593Smuzhiyun /* BCSR defines */ 15*4882a593Smuzhiyun /****************************************/ 16*4882a593Smuzhiyun #define BCSR6_UPC1_EN 0x80 17*4882a593Smuzhiyun #define BCSR6_UPC1_POS_EN 0x40 18*4882a593Smuzhiyun #define BCSR6_UPC1_ADDR_EN 0x20 19*4882a593Smuzhiyun #define BCSR6_UPC1_DEV2 0x10 20*4882a593Smuzhiyun #define BCSR6_SD_CARD_1BIT 0x08 21*4882a593Smuzhiyun #define BCSR6_SD_CARD_4BITS 0x04 22*4882a593Smuzhiyun #define BCSR6_TDM2G_EN 0x02 23*4882a593Smuzhiyun #define BCSR6_UCC7_RMII_EN 0x01 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define BCSR7_UCC1_GETH_EN 0x80 26*4882a593Smuzhiyun #define BCSR7_UCC1_RGMII_EN 0x40 27*4882a593Smuzhiyun #define BCSR7_UCC1_RTBI_EN 0x20 28*4882a593Smuzhiyun #define BCSR7_GETHRST_MRVL 0x04 29*4882a593Smuzhiyun #define BCSR7_BRD_WRT_PROTECT 0x02 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define BCSR8_UCC2_GETH_EN 0x80 32*4882a593Smuzhiyun #define BCSR8_UCC2_RGMII_EN 0x40 33*4882a593Smuzhiyun #define BCSR8_UCC2_RTBI_EN 0x20 34*4882a593Smuzhiyun #define BCSR8_UEM_MARVEL_RESET 0x02 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define BCSR9_UCC3_GETH_EN 0x80 37*4882a593Smuzhiyun #define BCSR9_UCC3_RGMII_EN 0x40 38*4882a593Smuzhiyun #define BCSR9_UCC3_RTBI_EN 0x20 39*4882a593Smuzhiyun #define BCSR9_UCC3_RMII_EN 0x10 40*4882a593Smuzhiyun #define BCSR9_UCC3_UEM_MICREL 0x01 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define BCSR10_UCC4_GETH_EN 0x80 43*4882a593Smuzhiyun #define BCSR10_UCC4_RGMII_EN 0x40 44*4882a593Smuzhiyun #define BCSR10_UCC4_RTBI_EN 0x20 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define BCSR11_LED0 0x40 47*4882a593Smuzhiyun #define BCSR11_LED1 0x20 48*4882a593Smuzhiyun #define BCSR11_LED2 0x10 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define BCSR12_UCC6_RMII_EN 0x20 51*4882a593Smuzhiyun #define BCSR12_UCC8_RMII_EN 0x20 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define BCSR15_SMII6_DIS 0x08 54*4882a593Smuzhiyun #define BCSR15_SMII8_DIS 0x04 55*4882a593Smuzhiyun #define BCSR15_QEUART_EN 0x01 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define BCSR16_UPC1_DEV2 0x02 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define BCSR17_nUSBEN 0x80 60*4882a593Smuzhiyun #define BCSR17_nUSBLOWSPD 0x40 61*4882a593Smuzhiyun #define BCSR17_USBVCC 0x20 62*4882a593Smuzhiyun #define BCSR17_USBMODE 0x10 63*4882a593Smuzhiyun #define BCSR17_FLASH_nWP 0x01 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /*BCSR Utils functions*/ 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun void enable_8569mds_flash_write(void); 68*4882a593Smuzhiyun void disable_8569mds_flash_write(void); 69*4882a593Smuzhiyun void enable_8569mds_qe_uec(void); 70*4882a593Smuzhiyun void disable_8569mds_brd_eeprom_write_protect(void); 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #endif /* __BCSR_H_ */ 73