1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2009 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/io.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include "bcsr.h"
11*4882a593Smuzhiyun
enable_8569mds_flash_write(void)12*4882a593Smuzhiyun void enable_8569mds_flash_write(void)
13*4882a593Smuzhiyun {
14*4882a593Smuzhiyun setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
15*4882a593Smuzhiyun }
16*4882a593Smuzhiyun
disable_8569mds_flash_write(void)17*4882a593Smuzhiyun void disable_8569mds_flash_write(void)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
20*4882a593Smuzhiyun }
21*4882a593Smuzhiyun
enable_8569mds_qe_uec(void)22*4882a593Smuzhiyun void enable_8569mds_qe_uec(void)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun #if defined(CONFIG_SYS_UCC_RGMII_MODE)
25*4882a593Smuzhiyun setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
26*4882a593Smuzhiyun BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
27*4882a593Smuzhiyun setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
28*4882a593Smuzhiyun BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
29*4882a593Smuzhiyun setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
30*4882a593Smuzhiyun BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
31*4882a593Smuzhiyun setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
32*4882a593Smuzhiyun BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
33*4882a593Smuzhiyun #elif defined(CONFIG_SYS_UCC_RMII_MODE)
34*4882a593Smuzhiyun /* Set UCC1-4 working at RMII mode */
35*4882a593Smuzhiyun clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
36*4882a593Smuzhiyun BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
37*4882a593Smuzhiyun clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
38*4882a593Smuzhiyun BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
39*4882a593Smuzhiyun clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
40*4882a593Smuzhiyun BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
41*4882a593Smuzhiyun clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
42*4882a593Smuzhiyun BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
43*4882a593Smuzhiyun setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), BCSR9_UCC3_RMII_EN);
44*4882a593Smuzhiyun #endif
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
disable_8569mds_brd_eeprom_write_protect(void)47*4882a593Smuzhiyun void disable_8569mds_brd_eeprom_write_protect(void)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), BCSR7_BRD_WRT_PROTECT);
50*4882a593Smuzhiyun }
51