1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2008 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2000 5*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <common.h> 11*4882a593Smuzhiyun #include <asm/mmu.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct fsl_e_tlb_entry tlb_table[] = { 14*4882a593Smuzhiyun /* TLB 0 - for temp stack in cache */ 15*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 16*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 17*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 18*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 19*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 20*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 21*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 22*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 23*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 24*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 25*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 26*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* TLB 1 Initializations */ 29*4882a593Smuzhiyun /* 30*4882a593Smuzhiyun * TLBe 0: 16M Non-cacheable, guarded 31*4882a593Smuzhiyun * 0xff000000 16M FLASH (upper half) 32*4882a593Smuzhiyun * Out of reset this entry is only 4K. 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, CONFIG_SYS_FLASH_BASE + 0x1000000, 35*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 36*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_16M, 1), 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* 39*4882a593Smuzhiyun * TLBe 1: 16M Non-cacheable, guarded 40*4882a593Smuzhiyun * 0xfe000000 16M FLASH (lower half) 41*4882a593Smuzhiyun */ 42*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, 43*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 44*4882a593Smuzhiyun 0, 1, BOOKE_PAGESZ_16M, 1), 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* 47*4882a593Smuzhiyun * TLBe 2: 1G Non-cacheable, guarded 48*4882a593Smuzhiyun * 0x80000000 512M PCI1 MEM 49*4882a593Smuzhiyun * 0xa0000000 512M PCIe MEM 50*4882a593Smuzhiyun */ 51*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, 52*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 53*4882a593Smuzhiyun 0, 2, BOOKE_PAGESZ_1G, 1), 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* 56*4882a593Smuzhiyun * TLBe 3: 64M Non-cacheable, guarded 57*4882a593Smuzhiyun * 0xe000_0000 1M CCSRBAR 58*4882a593Smuzhiyun * 0xe200_0000 8M PCI1 IO 59*4882a593Smuzhiyun * 0xe280_0000 8M PCIe IO 60*4882a593Smuzhiyun */ 61*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 62*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 63*4882a593Smuzhiyun 0, 3, BOOKE_PAGESZ_64M, 1), 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* 66*4882a593Smuzhiyun * TLBe 4: 64M Cacheable, non-guarded 67*4882a593Smuzhiyun * 0xf000_0000 64M LBC SDRAM 68*4882a593Smuzhiyun */ 69*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, 70*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 71*4882a593Smuzhiyun 0, 4, BOOKE_PAGESZ_64M, 1), 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* 74*4882a593Smuzhiyun * TLBe 5: 256K Non-cacheable, guarded 75*4882a593Smuzhiyun * 0xf8000000 32K BCSR 76*4882a593Smuzhiyun * 0xf8008000 32K PIB (CS4) 77*4882a593Smuzhiyun * 0xf8010000 32K PIB (CS5) 78*4882a593Smuzhiyun */ 79*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE, 80*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 81*4882a593Smuzhiyun 0, 5, BOOKE_PAGESZ_256K, 1), 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun int num_tlb_entries = ARRAY_SIZE(tlb_table); 85