1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2007 Freescale Semiconductor. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __BCSR_H_ 8*4882a593Smuzhiyun #define __BCSR_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <common.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* BCSR Bit definitions 13*4882a593Smuzhiyun * BCSR 0 * 14*4882a593Smuzhiyun 0:3 ccb sys pll 15*4882a593Smuzhiyun 4:6 cfg core pll 16*4882a593Smuzhiyun 7 cfg boot seq 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun * BCSR 1 * 19*4882a593Smuzhiyun 0:2 cfg rom lock 20*4882a593Smuzhiyun 3:5 cfg host agent 21*4882a593Smuzhiyun 6 PCI IO 22*4882a593Smuzhiyun 7 cfg RIO size 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun * BCSR 2 * 25*4882a593Smuzhiyun 0:4 QE PLL 26*4882a593Smuzhiyun 5 QE clock 27*4882a593Smuzhiyun 6 cfg PCI arbiter 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun * BCSR 3 * 30*4882a593Smuzhiyun 0 TSEC1 reduce 31*4882a593Smuzhiyun 1 TSEC2 reduce 32*4882a593Smuzhiyun 2:3 TSEC1 protocol 33*4882a593Smuzhiyun 4:5 TSEC2 protocol 34*4882a593Smuzhiyun 6 PHY1 slave 35*4882a593Smuzhiyun 7 PHY2 slave 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun * BCSR 4 * 38*4882a593Smuzhiyun 4 clock enable 39*4882a593Smuzhiyun 5 boot EPROM 40*4882a593Smuzhiyun 6 GETH transactive reset 41*4882a593Smuzhiyun 7 BRD write potect 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun * BCSR 5 * 44*4882a593Smuzhiyun 1:3 Leds 1-3 45*4882a593Smuzhiyun 4 UPC1 enable 46*4882a593Smuzhiyun 5 UPC2 enable 47*4882a593Smuzhiyun 6 UPC2 pos 48*4882a593Smuzhiyun 7 RS232 enable 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun * BCSR 6 * 51*4882a593Smuzhiyun 0 CFG ver 0 52*4882a593Smuzhiyun 1 CFG ver 1 53*4882a593Smuzhiyun 6 Register config led 54*4882a593Smuzhiyun 7 Power on reset 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun * BCSR 7 * 57*4882a593Smuzhiyun 2 board host mode indication 58*4882a593Smuzhiyun 5 enable TSEC1 PHY 59*4882a593Smuzhiyun 6 enable TSEC2 PHY 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun * BCSR 8 * 62*4882a593Smuzhiyun 0 UCC GETH1 enable 63*4882a593Smuzhiyun 1 UCC GMII enable 64*4882a593Smuzhiyun 3 UCC TBI enable 65*4882a593Smuzhiyun 5 UCC MII enable 66*4882a593Smuzhiyun 7 Real time clock reset 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun * BCSR 9 * 69*4882a593Smuzhiyun 0 UCC2 GETH enable 70*4882a593Smuzhiyun 1 UCC2 GMII enable 71*4882a593Smuzhiyun 3 UCC2 TBI enable 72*4882a593Smuzhiyun 5 UCC2 MII enable 73*4882a593Smuzhiyun 6 Ready only - indicate flash ready after burning 74*4882a593Smuzhiyun 7 Flash write protect 75*4882a593Smuzhiyun */ 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define BCSR_UCC1_GETH_EN (0x1 << 7) 78*4882a593Smuzhiyun #define BCSR_UCC2_GETH_EN (0x1 << 7) 79*4882a593Smuzhiyun #define BCSR_UCC1_MODE_MSK (0x3 << 4) 80*4882a593Smuzhiyun #define BCSR_UCC2_MODE_MSK (0x3 << 0) 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /*BCSR Utils functions*/ 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun void enable_8568mds_duart(void); 85*4882a593Smuzhiyun void enable_8568mds_flash_write(void); 86*4882a593Smuzhiyun void disable_8568mds_flash_write(void); 87*4882a593Smuzhiyun void enable_8568mds_qe_mdio(void); 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2) 90*4882a593Smuzhiyun void reset_8568mds_uccs(void); 91*4882a593Smuzhiyun #endif 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #endif /* __BCSR_H_ */ 94