1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2007 Freescale Semiconductor. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <common.h> 8*4882a593Smuzhiyun #include <asm/io.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include "bcsr.h" 11*4882a593Smuzhiyun enable_8568mds_duart(void)12*4882a593Smuzhiyunvoid enable_8568mds_duart(void) 13*4882a593Smuzhiyun { 14*4882a593Smuzhiyun volatile uint* duart_mux = (uint *)(CONFIG_SYS_CCSRBAR + 0xe0060); 15*4882a593Smuzhiyun volatile uint* devices = (uint *)(CONFIG_SYS_CCSRBAR + 0xe0070); 16*4882a593Smuzhiyun volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun *duart_mux = 0x80000000; /* Set the mux to Duart on PMUXCR */ 19*4882a593Smuzhiyun *devices = 0; /* Enable all peripheral devices */ 20*4882a593Smuzhiyun bcsr[5] |= 0x01; /* Enable Duart in BCSR*/ 21*4882a593Smuzhiyun } 22*4882a593Smuzhiyun enable_8568mds_flash_write(void)23*4882a593Smuzhiyunvoid enable_8568mds_flash_write(void) 24*4882a593Smuzhiyun { 25*4882a593Smuzhiyun volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun bcsr[9] |= 0x01; 28*4882a593Smuzhiyun } 29*4882a593Smuzhiyun disable_8568mds_flash_write(void)30*4882a593Smuzhiyunvoid disable_8568mds_flash_write(void) 31*4882a593Smuzhiyun { 32*4882a593Smuzhiyun volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun bcsr[9] &= ~(0x01); 35*4882a593Smuzhiyun } 36*4882a593Smuzhiyun enable_8568mds_qe_mdio(void)37*4882a593Smuzhiyunvoid enable_8568mds_qe_mdio(void) 38*4882a593Smuzhiyun { 39*4882a593Smuzhiyun u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun bcsr[7] |= 0x01; 42*4882a593Smuzhiyun } 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2) reset_8568mds_uccs(void)45*4882a593Smuzhiyunvoid reset_8568mds_uccs(void) 46*4882a593Smuzhiyun { 47*4882a593Smuzhiyun volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* Turn off UCC1 & UCC2 */ 50*4882a593Smuzhiyun out_8(&bcsr[8], in_8(&bcsr[8]) & ~BCSR_UCC1_GETH_EN); 51*4882a593Smuzhiyun out_8(&bcsr[9], in_8(&bcsr[9]) & ~BCSR_UCC2_GETH_EN); 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* Mode is RGMII, all bits clear */ 54*4882a593Smuzhiyun out_8(&bcsr[11], in_8(&bcsr[11]) & ~(BCSR_UCC1_MODE_MSK | 55*4882a593Smuzhiyun BCSR_UCC2_MODE_MSK)); 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* Turn UCC1 & UCC2 on */ 58*4882a593Smuzhiyun out_8(&bcsr[8], in_8(&bcsr[8]) | BCSR_UCC1_GETH_EN); 59*4882a593Smuzhiyun out_8(&bcsr[9], in_8(&bcsr[9]) | BCSR_UCC2_GETH_EN); 60*4882a593Smuzhiyun } 61*4882a593Smuzhiyun #endif 62