1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2008, 2011 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2000 5*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <common.h> 11*4882a593Smuzhiyun #include <asm/mmu.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct fsl_e_tlb_entry tlb_table[] = { 14*4882a593Smuzhiyun /* TLB 0 - for temp stack in cache */ 15*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 16*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 17*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 18*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 19*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 20*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 21*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 22*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 23*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 24*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 25*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 26*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* TLB 1 */ 29*4882a593Smuzhiyun /* 30*4882a593Smuzhiyun * Entry 0: 31*4882a593Smuzhiyun * FLASH(cover boot page) 16M Non-cacheable, guarded 32*4882a593Smuzhiyun */ 33*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 34*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 35*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_16M, 1), 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* 38*4882a593Smuzhiyun * Entry 1: 39*4882a593Smuzhiyun * CCSRBAR 1M Non-cacheable, guarded 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 42*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 43*4882a593Smuzhiyun 0, 1, BOOKE_PAGESZ_1M, 1), 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* 46*4882a593Smuzhiyun * Entry 2: 47*4882a593Smuzhiyun * LBC SDRAM 64M Cacheable, non-guarded 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, 50*4882a593Smuzhiyun CONFIG_SYS_LBC_SDRAM_BASE_PHYS, 51*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 52*4882a593Smuzhiyun 0, 2, BOOKE_PAGESZ_64M, 1), 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* 55*4882a593Smuzhiyun * Entry 3: 56*4882a593Smuzhiyun * CADMUS registers 1M Non-cacheable, guarded 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR_PHYS, 59*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 60*4882a593Smuzhiyun 0, 3, BOOKE_PAGESZ_1M, 1), 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* 63*4882a593Smuzhiyun * Entry 4: 64*4882a593Smuzhiyun * PCI and PCIe MEM 1G Non-cacheable, guarded 65*4882a593Smuzhiyun */ 66*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, 67*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 68*4882a593Smuzhiyun 0, 4, BOOKE_PAGESZ_1G, 1), 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* 71*4882a593Smuzhiyun * Entry 5: 72*4882a593Smuzhiyun * PCI1 IO 1M Non-cacheable, guarded 73*4882a593Smuzhiyun */ 74*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS, 75*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 76*4882a593Smuzhiyun 0, 5, BOOKE_PAGESZ_1M, 1), 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* 79*4882a593Smuzhiyun * Entry 6: 80*4882a593Smuzhiyun * PCIe IO 1M Non-cacheable, guarded 81*4882a593Smuzhiyun */ 82*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 83*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 84*4882a593Smuzhiyun 0, 6, BOOKE_PAGESZ_1M, 1), 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun int num_tlb_entries = ARRAY_SIZE(tlb_table); 88