1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2008 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2000 5*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <common.h> 11*4882a593Smuzhiyun #include <asm/mmu.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct fsl_e_tlb_entry tlb_table[] = { 14*4882a593Smuzhiyun /* TLB 0 - for temp stack in cache */ 15*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 16*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 17*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 18*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 19*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 20*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 21*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 22*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 23*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 24*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 25*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 26*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* 29*4882a593Smuzhiyun * TLB 0: 16M Non-cacheable, guarded 30*4882a593Smuzhiyun * 0xff000000 16M FLASH 31*4882a593Smuzhiyun * Out of reset this entry is only 4K. 32*4882a593Smuzhiyun */ 33*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, 34*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 35*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_16M, 1), 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* 38*4882a593Smuzhiyun * TLB 1: 256M Non-cacheable, guarded 39*4882a593Smuzhiyun * 0x80000000 256M PCI1 MEM First half 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, 42*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 43*4882a593Smuzhiyun 0, 1, BOOKE_PAGESZ_256M, 1), 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* 46*4882a593Smuzhiyun * TLB 2: 256M Non-cacheable, guarded 47*4882a593Smuzhiyun * 0x90000000 256M PCI1 MEM Second half 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, 50*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 51*4882a593Smuzhiyun 0, 2, BOOKE_PAGESZ_256M, 1), 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* 54*4882a593Smuzhiyun * TLB 3: 256M Non-cacheable, guarded 55*4882a593Smuzhiyun * 0xa0000000 256M PCI2 MEM First half 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS, 58*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 59*4882a593Smuzhiyun 0, 3, BOOKE_PAGESZ_256M, 1), 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* 62*4882a593Smuzhiyun * TLB 4: 256M Non-cacheable, guarded 63*4882a593Smuzhiyun * 0xb0000000 256M PCI2 MEM Second half 64*4882a593Smuzhiyun */ 65*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, 66*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 67*4882a593Smuzhiyun 0, 4, BOOKE_PAGESZ_256M, 1), 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* 70*4882a593Smuzhiyun * TLB 5: 64M Non-cacheable, guarded 71*4882a593Smuzhiyun * 0xe000_0000 1M CCSRBAR 72*4882a593Smuzhiyun * 0xe200_0000 16M PCI1 IO 73*4882a593Smuzhiyun * 0xe300_0000 16M PCI2 IO 74*4882a593Smuzhiyun */ 75*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 76*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 77*4882a593Smuzhiyun 0, 5, BOOKE_PAGESZ_64M, 1), 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* 80*4882a593Smuzhiyun * TLB 6: 64M Cacheable, non-guarded 81*4882a593Smuzhiyun * 0xf000_0000 64M LBC SDRAM 82*4882a593Smuzhiyun */ 83*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, 84*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 85*4882a593Smuzhiyun 0, 6, BOOKE_PAGESZ_64M, 1), 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* 88*4882a593Smuzhiyun * TLB 7: 1M Non-cacheable, guarded 89*4882a593Smuzhiyun * 0xf8000000 1M CADMUS registers 90*4882a593Smuzhiyun */ 91*4882a593Smuzhiyun SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR, 92*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 93*4882a593Smuzhiyun 0, 7, BOOKE_PAGESZ_1M, 1), 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun int num_tlb_entries = ARRAY_SIZE(tlb_table); 97