1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2008 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2000 5*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <common.h> 11*4882a593Smuzhiyun #include <asm/mmu.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct fsl_e_tlb_entry tlb_table[] = { 14*4882a593Smuzhiyun /* TLB 0 - for temp stack in cache */ 15*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 16*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 17*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 18*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 19*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 20*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 21*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 22*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 23*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 24*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 25*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 26*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS, 29*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 30*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* TLB 1 */ 33*4882a593Smuzhiyun /* *I*G* - CCSRBAR */ 34*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 35*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 36*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_1M, 1), 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* W**G* - Flash/promjet, localbus */ 39*4882a593Smuzhiyun /* This will be changed to *I*G* after relocation to RAM. */ 40*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 41*4882a593Smuzhiyun MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 42*4882a593Smuzhiyun 0, 1, BOOKE_PAGESZ_256M, 1), 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* *I*G* - PCI */ 45*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, 46*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 47*4882a593Smuzhiyun 0, 2, BOOKE_PAGESZ_1G, 1), 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* *I*G* - PCI I/O */ 50*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS, 51*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 52*4882a593Smuzhiyun 0, 3, BOOKE_PAGESZ_256K, 1), 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* *I*G - NAND */ 55*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 56*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 57*4882a593Smuzhiyun 0, 4, BOOKE_PAGESZ_1M, 1), 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 60*4882a593Smuzhiyun /* *I*G - L2SRAM */ 61*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, 62*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 63*4882a593Smuzhiyun 0, 5, BOOKE_PAGESZ_256K, 1), 64*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, 65*4882a593Smuzhiyun CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, 66*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 67*4882a593Smuzhiyun 0, 6, BOOKE_PAGESZ_256K, 1), 68*4882a593Smuzhiyun #endif 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun int num_tlb_entries = ARRAY_SIZE(tlb_table); 72