1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2008 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <common.h> 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <fsl_ddr_sdram.h> 10*4882a593Smuzhiyun #include <fsl_ddr_dimm_params.h> 11*4882a593Smuzhiyun fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)12*4882a593Smuzhiyunvoid fsl_ddr_board_options(memctl_options_t *popts, 13*4882a593Smuzhiyun dimm_params_t *pdimm, 14*4882a593Smuzhiyun unsigned int ctrl_num) 15*4882a593Smuzhiyun { 16*4882a593Smuzhiyun /* 17*4882a593Smuzhiyun * Factors to consider for clock adjust: 18*4882a593Smuzhiyun * - number of chips on bus 19*4882a593Smuzhiyun * - position of slot 20*4882a593Smuzhiyun * - DDR1 vs. DDR2? 21*4882a593Smuzhiyun * - ??? 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * This needs to be determined on a board-by-board basis. 24*4882a593Smuzhiyun * 0110 3/4 cycle late 25*4882a593Smuzhiyun * 0111 7/8 cycle late 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun popts->clk_adjust = 7; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* 30*4882a593Smuzhiyun * Factors to consider for CPO: 31*4882a593Smuzhiyun * - frequency 32*4882a593Smuzhiyun * - ddr1 vs. ddr2 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun popts->cpo_override = 10; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* 37*4882a593Smuzhiyun * Factors to consider for write data delay: 38*4882a593Smuzhiyun * - number of DIMMs 39*4882a593Smuzhiyun * 40*4882a593Smuzhiyun * 1 = 1/4 clock delay 41*4882a593Smuzhiyun * 2 = 1/2 clock delay 42*4882a593Smuzhiyun * 3 = 3/4 clock delay 43*4882a593Smuzhiyun * 4 = 1 clock delay 44*4882a593Smuzhiyun * 5 = 5/4 clock delay 45*4882a593Smuzhiyun * 6 = 3/2 clock delay 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun popts->write_data_delay = 3; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* 50*4882a593Smuzhiyun * Factors to consider for half-strength driver enable: 51*4882a593Smuzhiyun * - number of DIMMs installed 52*4882a593Smuzhiyun */ 53*4882a593Smuzhiyun popts->half_strength_driver_enable = 0; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* 56*4882a593Smuzhiyun * For wake up arp feature, we need enable auto self refresh 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun popts->auto_self_refresh_en = 1; 59*4882a593Smuzhiyun popts->sr_it = 0x6; 60*4882a593Smuzhiyun } 61