1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <mpc83xx.h>
9*4882a593Smuzhiyun #include <pci.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun static struct pci_region pci_regions[] = {
13*4882a593Smuzhiyun {
14*4882a593Smuzhiyun bus_start: CONFIG_SYS_PCI_MEM_BASE,
15*4882a593Smuzhiyun phys_start: CONFIG_SYS_PCI_MEM_PHYS,
16*4882a593Smuzhiyun size: CONFIG_SYS_PCI_MEM_SIZE,
17*4882a593Smuzhiyun flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
18*4882a593Smuzhiyun },
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun bus_start: CONFIG_SYS_PCI_MMIO_BASE,
21*4882a593Smuzhiyun phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
22*4882a593Smuzhiyun size: CONFIG_SYS_PCI_MMIO_SIZE,
23*4882a593Smuzhiyun flags: PCI_REGION_MEM
24*4882a593Smuzhiyun },
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun bus_start: CONFIG_SYS_PCI_IO_BASE,
27*4882a593Smuzhiyun phys_start: CONFIG_SYS_PCI_IO_PHYS,
28*4882a593Smuzhiyun size: CONFIG_SYS_PCI_IO_SIZE,
29*4882a593Smuzhiyun flags: PCI_REGION_IO
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun static struct pci_region pcie_regions_0[] = {
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
36*4882a593Smuzhiyun .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
37*4882a593Smuzhiyun .size = CONFIG_SYS_PCIE1_MEM_SIZE,
38*4882a593Smuzhiyun .flags = PCI_REGION_MEM,
39*4882a593Smuzhiyun },
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
42*4882a593Smuzhiyun .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
43*4882a593Smuzhiyun .size = CONFIG_SYS_PCIE1_IO_SIZE,
44*4882a593Smuzhiyun .flags = PCI_REGION_IO,
45*4882a593Smuzhiyun },
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun static struct pci_region pcie_regions_1[] = {
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
51*4882a593Smuzhiyun .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
52*4882a593Smuzhiyun .size = CONFIG_SYS_PCIE2_MEM_SIZE,
53*4882a593Smuzhiyun .flags = PCI_REGION_MEM,
54*4882a593Smuzhiyun },
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
57*4882a593Smuzhiyun .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
58*4882a593Smuzhiyun .size = CONFIG_SYS_PCIE2_IO_SIZE,
59*4882a593Smuzhiyun .flags = PCI_REGION_IO,
60*4882a593Smuzhiyun },
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun
pci_init_board(void)63*4882a593Smuzhiyun void pci_init_board(void)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
66*4882a593Smuzhiyun volatile sysconf83xx_t *sysconf = &immr->sysconf;
67*4882a593Smuzhiyun volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
68*4882a593Smuzhiyun volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
69*4882a593Smuzhiyun volatile law83xx_t *pcie_law = sysconf->pcielaw;
70*4882a593Smuzhiyun struct pci_region *reg[] = { pci_regions };
71*4882a593Smuzhiyun struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
72*4882a593Smuzhiyun u32 spridr = in_be32(&immr->sysconf.spridr);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* Enable all 5 PCI_CLK_OUTPUTS */
75*4882a593Smuzhiyun clk->occr |= 0xf8000000;
76*4882a593Smuzhiyun udelay(2000);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /* Configure PCI Local Access Windows */
79*4882a593Smuzhiyun pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
80*4882a593Smuzhiyun pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
83*4882a593Smuzhiyun pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun mpc83xx_pci_init(1, reg);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* There is no PEX in MPC8379 parts. */
88*4882a593Smuzhiyun if (PARTID_NO_E(spridr) == SPR_8379)
89*4882a593Smuzhiyun return;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun /* Configure the clock for PCIE controller */
92*4882a593Smuzhiyun clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
93*4882a593Smuzhiyun SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /* Deassert the resets in the control register */
96*4882a593Smuzhiyun out_be32(&sysconf->pecr1, 0xE0008000);
97*4882a593Smuzhiyun out_be32(&sysconf->pecr2, 0xE0008000);
98*4882a593Smuzhiyun udelay(2000);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun /* Configure PCI Express Local Access Windows */
101*4882a593Smuzhiyun out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
102*4882a593Smuzhiyun out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
105*4882a593Smuzhiyun out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun mpc83xx_pcie_init(2, pcie_reg);
108*4882a593Smuzhiyun }
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