1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <asm/mmu.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun #include <mpc83xx.h>
12*4882a593Smuzhiyun #include <pci.h>
13*4882a593Smuzhiyun #include <i2c.h>
14*4882a593Smuzhiyun #include <asm/fsl_i2c.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun static struct pci_region pci1_regions[] = {
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun bus_start: CONFIG_SYS_PCI1_MEM_BASE,
21*4882a593Smuzhiyun phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
22*4882a593Smuzhiyun size: CONFIG_SYS_PCI1_MEM_SIZE,
23*4882a593Smuzhiyun flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
24*4882a593Smuzhiyun },
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun bus_start: CONFIG_SYS_PCI1_IO_BASE,
27*4882a593Smuzhiyun phys_start: CONFIG_SYS_PCI1_IO_PHYS,
28*4882a593Smuzhiyun size: CONFIG_SYS_PCI1_IO_SIZE,
29*4882a593Smuzhiyun flags: PCI_REGION_IO
30*4882a593Smuzhiyun },
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
33*4882a593Smuzhiyun phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
34*4882a593Smuzhiyun size: CONFIG_SYS_PCI1_MMIO_SIZE,
35*4882a593Smuzhiyun flags: PCI_REGION_MEM
36*4882a593Smuzhiyun },
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #ifdef CONFIG_MPC83XX_PCI2
40*4882a593Smuzhiyun static struct pci_region pci2_regions[] = {
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun bus_start: CONFIG_SYS_PCI2_MEM_BASE,
43*4882a593Smuzhiyun phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
44*4882a593Smuzhiyun size: CONFIG_SYS_PCI2_MEM_SIZE,
45*4882a593Smuzhiyun flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
46*4882a593Smuzhiyun },
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun bus_start: CONFIG_SYS_PCI2_IO_BASE,
49*4882a593Smuzhiyun phys_start: CONFIG_SYS_PCI2_IO_PHYS,
50*4882a593Smuzhiyun size: CONFIG_SYS_PCI2_IO_SIZE,
51*4882a593Smuzhiyun flags: PCI_REGION_IO
52*4882a593Smuzhiyun },
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
55*4882a593Smuzhiyun phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
56*4882a593Smuzhiyun size: CONFIG_SYS_PCI2_MMIO_SIZE,
57*4882a593Smuzhiyun flags: PCI_REGION_MEM
58*4882a593Smuzhiyun },
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun #endif
61*4882a593Smuzhiyun
pci_init_board(void)62*4882a593Smuzhiyun void pci_init_board(void)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
65*4882a593Smuzhiyun volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
66*4882a593Smuzhiyun volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
67*4882a593Smuzhiyun #ifndef CONFIG_MPC83XX_PCI2
68*4882a593Smuzhiyun struct pci_region *reg[] = { pci1_regions };
69*4882a593Smuzhiyun #else
70*4882a593Smuzhiyun struct pci_region *reg[] = { pci1_regions, pci2_regions };
71*4882a593Smuzhiyun #endif
72*4882a593Smuzhiyun u8 reg8;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun #if defined(CONFIG_SYS_I2C)
75*4882a593Smuzhiyun i2c_set_bus_num(1);
76*4882a593Smuzhiyun /* Read the PCI_M66EN jumper setting */
77*4882a593Smuzhiyun if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0) ||
78*4882a593Smuzhiyun (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0)) {
79*4882a593Smuzhiyun if (reg8 & I2C_8574_PCI66)
80*4882a593Smuzhiyun clk->occr = 0xff000000; /* 66 MHz PCI */
81*4882a593Smuzhiyun else
82*4882a593Smuzhiyun clk->occr = 0xff600001; /* 33 MHz PCI */
83*4882a593Smuzhiyun } else {
84*4882a593Smuzhiyun clk->occr = 0xff600001; /* 33 MHz PCI */
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun #else
87*4882a593Smuzhiyun clk->occr = 0xff000000; /* 66 MHz PCI */
88*4882a593Smuzhiyun #endif
89*4882a593Smuzhiyun udelay(2000);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun /* Configure PCI Local Access Windows */
92*4882a593Smuzhiyun pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
93*4882a593Smuzhiyun pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
96*4882a593Smuzhiyun pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun udelay(2000);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun #ifndef CONFIG_MPC83XX_PCI2
101*4882a593Smuzhiyun mpc83xx_pci_init(1, reg);
102*4882a593Smuzhiyun #else
103*4882a593Smuzhiyun mpc83xx_pci_init(2, reg);
104*4882a593Smuzhiyun #endif
105*4882a593Smuzhiyun }
106