1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2011 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <fsl_ddr_sdram.h>
10*4882a593Smuzhiyun #include <fsl_ddr_dimm_params.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun struct board_specific_parameters {
13*4882a593Smuzhiyun u32 n_ranks;
14*4882a593Smuzhiyun u32 datarate_mhz_high;
15*4882a593Smuzhiyun u32 clk_adjust;
16*4882a593Smuzhiyun u32 cpo;
17*4882a593Smuzhiyun u32 write_data_delay;
18*4882a593Smuzhiyun u32 force_2t;
19*4882a593Smuzhiyun };
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /*
22*4882a593Smuzhiyun * This table contains all valid speeds we want to override with board
23*4882a593Smuzhiyun * specific parameters. datarate_mhz_high values need to be in ascending order
24*4882a593Smuzhiyun * for each n_ranks group.
25*4882a593Smuzhiyun */
26*4882a593Smuzhiyun static const struct board_specific_parameters udimm0[] = {
27*4882a593Smuzhiyun /*
28*4882a593Smuzhiyun * memory controller 0
29*4882a593Smuzhiyun * num| hi| clk| cpo|wrdata|2T
30*4882a593Smuzhiyun * ranks| mhz|adjst| | delay|
31*4882a593Smuzhiyun */
32*4882a593Smuzhiyun {2, 300, 4, 4, 2, 0},
33*4882a593Smuzhiyun {2, 365, 4, 6, 2, 0},
34*4882a593Smuzhiyun {2, 450, 4, 7, 2, 0},
35*4882a593Smuzhiyun {2, 850, 4, 31, 2, 0},
36*4882a593Smuzhiyun {1, 300, 4, 4, 2, 0},
37*4882a593Smuzhiyun {1, 365, 4, 6, 2, 0},
38*4882a593Smuzhiyun {1, 450, 4, 7, 2, 0},
39*4882a593Smuzhiyun {1, 850, 4, 31, 2, 0},
40*4882a593Smuzhiyun {}
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)43*4882a593Smuzhiyun void fsl_ddr_board_options(memctl_options_t *popts,
44*4882a593Smuzhiyun dimm_params_t *pdimm,
45*4882a593Smuzhiyun unsigned int ctrl_num)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
48*4882a593Smuzhiyun unsigned int i;
49*4882a593Smuzhiyun ulong ddr_freq;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun if (ctrl_num != 0) /* we have only one controller */
52*4882a593Smuzhiyun return;
53*4882a593Smuzhiyun for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
54*4882a593Smuzhiyun if (pdimm[i].n_ranks)
55*4882a593Smuzhiyun break;
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */
58*4882a593Smuzhiyun return;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun pbsp = udimm0;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
63*4882a593Smuzhiyun * freqency and n_banks specified in board_specific_parameters table.
64*4882a593Smuzhiyun */
65*4882a593Smuzhiyun ddr_freq = get_ddr_freq(0) / 1000000;
66*4882a593Smuzhiyun while (pbsp->datarate_mhz_high) {
67*4882a593Smuzhiyun if (pbsp->n_ranks == pdimm[i].n_ranks) {
68*4882a593Smuzhiyun if (ddr_freq <= pbsp->datarate_mhz_high) {
69*4882a593Smuzhiyun popts->clk_adjust = pbsp->clk_adjust;
70*4882a593Smuzhiyun popts->cpo_override = pbsp->cpo;
71*4882a593Smuzhiyun popts->write_data_delay =
72*4882a593Smuzhiyun pbsp->write_data_delay;
73*4882a593Smuzhiyun popts->twot_en = pbsp->force_2t;
74*4882a593Smuzhiyun goto found;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun pbsp_highest = pbsp;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun pbsp++;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun if (pbsp_highest) {
82*4882a593Smuzhiyun printf("Error: board specific timing not found "
83*4882a593Smuzhiyun "for data rate %lu MT/s!\n"
84*4882a593Smuzhiyun "Trying to use the highest speed (%u) parameters\n",
85*4882a593Smuzhiyun ddr_freq, pbsp_highest->datarate_mhz_high);
86*4882a593Smuzhiyun popts->clk_adjust = pbsp_highest->clk_adjust;
87*4882a593Smuzhiyun popts->cpo_override = pbsp_highest->cpo;
88*4882a593Smuzhiyun popts->write_data_delay = pbsp_highest->write_data_delay;
89*4882a593Smuzhiyun popts->twot_en = pbsp_highest->force_2t;
90*4882a593Smuzhiyun } else {
91*4882a593Smuzhiyun panic("DIMM is not supported by this board");
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun found:
95*4882a593Smuzhiyun /*
96*4882a593Smuzhiyun * Factors to consider for half-strength driver enable:
97*4882a593Smuzhiyun * - number of DIMMs installed
98*4882a593Smuzhiyun */
99*4882a593Smuzhiyun popts->half_strength_driver_enable = 0;
100*4882a593Smuzhiyun popts->dqs_config = 0; /* only true DQS signal is used on board */
101*4882a593Smuzhiyun }
102