1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun /*
8*4882a593Smuzhiyun * PCI Configuration space access support for MPC83xx PCI Bridge
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun #include <asm/mmu.h>
11*4882a593Smuzhiyun #include <asm/io.h>
12*4882a593Smuzhiyun #include <common.h>
13*4882a593Smuzhiyun #include <mpc83xx.h>
14*4882a593Smuzhiyun #include <pci.h>
15*4882a593Smuzhiyun #include <i2c.h>
16*4882a593Smuzhiyun #include <asm/fsl_i2c.h>
17*4882a593Smuzhiyun #include "../common/pq-mds-pib.h"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun static struct pci_region pci1_regions[] = {
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun bus_start: CONFIG_SYS_PCI1_MEM_BASE,
24*4882a593Smuzhiyun phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
25*4882a593Smuzhiyun size: CONFIG_SYS_PCI1_MEM_SIZE,
26*4882a593Smuzhiyun flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
27*4882a593Smuzhiyun },
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun bus_start: CONFIG_SYS_PCI1_IO_BASE,
30*4882a593Smuzhiyun phys_start: CONFIG_SYS_PCI1_IO_PHYS,
31*4882a593Smuzhiyun size: CONFIG_SYS_PCI1_IO_SIZE,
32*4882a593Smuzhiyun flags: PCI_REGION_IO
33*4882a593Smuzhiyun },
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
36*4882a593Smuzhiyun phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
37*4882a593Smuzhiyun size: CONFIG_SYS_PCI1_MMIO_SIZE,
38*4882a593Smuzhiyun flags: PCI_REGION_MEM
39*4882a593Smuzhiyun },
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #ifdef CONFIG_MPC83XX_PCI2
43*4882a593Smuzhiyun static struct pci_region pci2_regions[] = {
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun bus_start: CONFIG_SYS_PCI2_MEM_BASE,
46*4882a593Smuzhiyun phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
47*4882a593Smuzhiyun size: CONFIG_SYS_PCI2_MEM_SIZE,
48*4882a593Smuzhiyun flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
49*4882a593Smuzhiyun },
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun bus_start: CONFIG_SYS_PCI2_IO_BASE,
52*4882a593Smuzhiyun phys_start: CONFIG_SYS_PCI2_IO_PHYS,
53*4882a593Smuzhiyun size: CONFIG_SYS_PCI2_IO_SIZE,
54*4882a593Smuzhiyun flags: PCI_REGION_IO
55*4882a593Smuzhiyun },
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
58*4882a593Smuzhiyun phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
59*4882a593Smuzhiyun size: CONFIG_SYS_PCI2_MMIO_SIZE,
60*4882a593Smuzhiyun flags: PCI_REGION_MEM
61*4882a593Smuzhiyun },
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun #endif
64*4882a593Smuzhiyun
pci_init_board(void)65*4882a593Smuzhiyun void pci_init_board(void)
66*4882a593Smuzhiyun #ifdef CONFIG_PCISLAVE
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
69*4882a593Smuzhiyun volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
70*4882a593Smuzhiyun volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
71*4882a593Smuzhiyun struct pci_region *reg[] = { pci1_regions };
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /* Configure PCI Local Access Windows */
74*4882a593Smuzhiyun pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
75*4882a593Smuzhiyun pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
78*4882a593Smuzhiyun pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun mpc83xx_pci_init(1, reg);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /*
83*4882a593Smuzhiyun * Configure PCI Inbound Translation Windows
84*4882a593Smuzhiyun */
85*4882a593Smuzhiyun pci_ctrl[0].pitar0 = 0x0;
86*4882a593Smuzhiyun pci_ctrl[0].pibar0 = 0x0;
87*4882a593Smuzhiyun pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
88*4882a593Smuzhiyun PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun pci_ctrl[0].pitar1 = 0x0;
91*4882a593Smuzhiyun pci_ctrl[0].pibar1 = 0x0;
92*4882a593Smuzhiyun pci_ctrl[0].piebar1 = 0x0;
93*4882a593Smuzhiyun pci_ctrl[0].piwar1 &= ~PIWAR_EN;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun pci_ctrl[0].pitar2 = 0x0;
96*4882a593Smuzhiyun pci_ctrl[0].pibar2 = 0x0;
97*4882a593Smuzhiyun pci_ctrl[0].piebar2 = 0x0;
98*4882a593Smuzhiyun pci_ctrl[0].piwar2 &= ~PIWAR_EN;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun /* Unlock the configuration bit */
101*4882a593Smuzhiyun mpc83xx_pcislave_unlock(0);
102*4882a593Smuzhiyun printf("PCI: Agent mode enabled\n");
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun #else
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
107*4882a593Smuzhiyun volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
108*4882a593Smuzhiyun volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
109*4882a593Smuzhiyun #ifndef CONFIG_MPC83XX_PCI2
110*4882a593Smuzhiyun struct pci_region *reg[] = { pci1_regions };
111*4882a593Smuzhiyun #else
112*4882a593Smuzhiyun struct pci_region *reg[] = { pci1_regions, pci2_regions };
113*4882a593Smuzhiyun #endif
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun /* initialize the PCA9555PW IO expander on the PIB board */
116*4882a593Smuzhiyun pib_init();
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun #if defined(CONFIG_PCI_66M)
119*4882a593Smuzhiyun clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
120*4882a593Smuzhiyun printf("PCI clock is 66MHz\n");
121*4882a593Smuzhiyun #elif defined(CONFIG_PCI_33M)
122*4882a593Smuzhiyun clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
123*4882a593Smuzhiyun OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
124*4882a593Smuzhiyun printf("PCI clock is 33MHz\n");
125*4882a593Smuzhiyun #else
126*4882a593Smuzhiyun clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
127*4882a593Smuzhiyun printf("PCI clock is 66MHz\n");
128*4882a593Smuzhiyun #endif
129*4882a593Smuzhiyun udelay(2000);
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun /* Configure PCI Local Access Windows */
132*4882a593Smuzhiyun pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
133*4882a593Smuzhiyun pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
136*4882a593Smuzhiyun pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun udelay(2000);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun #ifndef CONFIG_MPC83XX_PCI2
141*4882a593Smuzhiyun mpc83xx_pci_init(1, reg);
142*4882a593Smuzhiyun #else
143*4882a593Smuzhiyun mpc83xx_pci_init(2, reg);
144*4882a593Smuzhiyun #endif
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun #endif /* CONFIG_PCISLAVE */
147