1*4882a593SmuzhiyunFreescale MPC832XEMDS Board 2*4882a593Smuzhiyun----------------------------------------- 3*4882a593Smuzhiyun1. Board Switches and Jumpers 4*4882a593Smuzhiyun1.0 There are five Dual-In-Line Packages(DIP) Switches on MPC832XE SYS board 5*4882a593Smuzhiyun For some reason, the HW designers describe the switch settings 6*4882a593Smuzhiyun in terms of 0 and 1, and then map that to physical switches where 7*4882a593Smuzhiyun the label "On" refers to logic 0 and "Off" is logic 1. 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun Switch bits are numbered 1 through, like, 4 6 8 or 10, but the 10*4882a593Smuzhiyun bits may contribute to signals that are numbered based at 0, 11*4882a593Smuzhiyun and some of those signals may be high-bit-number-0 too. Heed 12*4882a593Smuzhiyun well the names and labels and do not get confused. 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun "Off" == 1 15*4882a593Smuzhiyun "On" == 0 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun SW3 is switch 18 as silk-screened onto the board. 18*4882a593Smuzhiyun SW4[8] is the bit labeled 8 on Switch 4. 19*4882a593Smuzhiyun SW5[1:6] refers to bits labeled 1 through 6 in order on switch 5. 20*4882a593Smuzhiyun SW6[7:1] refers to bits labeled 7 through 1 in order on switch 6. 21*4882a593Smuzhiyun SW7[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On" 22*4882a593Smuzhiyun and bits labeled 8 is set as "Off". 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun1.1 For the MPC832XEMDS PROTO Board 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun First, make sure the board default setting is consistent with the document 27*4882a593Smuzhiyun shipped with your board. Then apply the following setting: 28*4882a593Smuzhiyun SW3[1-8]= 0000_1000 (core PLL setting, core enable) 29*4882a593Smuzhiyun SW4[1-8]= 0001_0010 (Flash boot on local bus, system PLL setting) 30*4882a593Smuzhiyun SW5[1-8]= 0010_0110 (Boot from high end) 31*4882a593Smuzhiyun SW6[1-8]= 0011_0100 (Flash boot on 16 bit local bus) 32*4882a593Smuzhiyun SW7[1-8]= 1000_0011 (QE PLL setting) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun ENET3/4 MII mode settings: 35*4882a593Smuzhiyun J1 1-2 (ETH3_TXER) 36*4882a593Smuzhiyun J2 2-3 (MII mode) 37*4882a593Smuzhiyun J3 2-3 (MII mode) 38*4882a593Smuzhiyun J4 2-3 (ADSL clockOscillator) 39*4882a593Smuzhiyun J5 1-2 (ETH4_TXER) 40*4882a593Smuzhiyun J6 2-3 (ClockOscillator) 41*4882a593Smuzhiyun JP1 removed (don't force PORESET) 42*4882a593Smuzhiyun JP2 mounted (ETH4/2 MII) 43*4882a593Smuzhiyun JP3 mounted (ETH3 MII) 44*4882a593Smuzhiyun JP4 mounted (HRCW from BCSR) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun ENET3/4 RMII mode settings: 47*4882a593Smuzhiyun J1 1-2 (ETH3_TXER) 48*4882a593Smuzhiyun J2 1-2 (RMII mode) 49*4882a593Smuzhiyun J3 1-2 (RMII mode) 50*4882a593Smuzhiyun J4 2-3 (ADSL clockOscillator) 51*4882a593Smuzhiyun J5 1-2 (ETH4_TXER) 52*4882a593Smuzhiyun J6 2-3 (ClockOscillator) 53*4882a593Smuzhiyun JP1 removed (don't force PORESET) 54*4882a593Smuzhiyun JP2 removed (ETH4/2 RMII) 55*4882a593Smuzhiyun JP3 removed (ETH3 RMII) 56*4882a593Smuzhiyun JP4 removed (HRCW from FLASH) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun on board Oscillator: 66M 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun2. Memory Map 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun2.1 The memory map should look pretty much like this: 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun 0x0000_0000 0x7fff_ffff DDR 2G 66*4882a593Smuzhiyun 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M 67*4882a593Smuzhiyun 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M 68*4882a593Smuzhiyun 0xc000_0000 0xdfff_ffff Empty 512M 69*4882a593Smuzhiyun 0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M 70*4882a593Smuzhiyun 0xe020_0000 0xe02f_ffff Empty 1M 71*4882a593Smuzhiyun 0xe030_0000 0xe03f_ffff PCI IO 1M 72*4882a593Smuzhiyun 0xe040_0000 0xefff_ffff Empty 252M 73*4882a593Smuzhiyun 0xf400_0000 0xf7ff_ffff Empty 64M 74*4882a593Smuzhiyun 0xf800_0000 0xf800_7fff BCSR on CS1 32K 75*4882a593Smuzhiyun 0xf800_8000 0xf800_ffff PIB CS2 32K 76*4882a593Smuzhiyun 0xf801_0000 0xf801_7fff PIB CS3 32K 77*4882a593Smuzhiyun 0xfe00_0000 0xfeff_ffff FLASH on CS0 16M 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun3. Definitions 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun3.1 Explanation of NEW definitions in: 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun include/configs/MPC832XEPB.h 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun CONFIG_MPC83xx MPC83xx family for MPC8349, MPC8360 and MPC832x 87*4882a593Smuzhiyun CONFIG_MPC832x MPC832x specific 88*4882a593Smuzhiyun CONFIG_MPC832XEMDS MPC832XEMDS board specific 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun4. Compilation 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun Assuming you're using BASH shell: 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun export CROSS_COMPILE=your-cross-compile-prefix 95*4882a593Smuzhiyun cd u-boot 96*4882a593Smuzhiyun make distclean 97*4882a593Smuzhiyun make MPC832XEMDS_config 98*4882a593Smuzhiyun make 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun MPC832x support PCI 33MHz and PCI 66MHz, to make U-Boot support PCI: 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun 1)Make sure the DIP SW support PCI mode as described in Section 1.1. 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun 2)To Make U-Boot image support PCI 33MHz, use 105*4882a593Smuzhiyun Make MPC832XEMDS_HOST_33_config 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun 3)To Make U-Boot image support PCI 66MHz, use 108*4882a593Smuzhiyun Make MPC832XEMDS_HOST_66M_config 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun5. Downloading and Flashing Images 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun5.0 Download over network: 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun tftp 10000 u-boot.bin 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun5.1 Reflash U-Boot Image using U-Boot 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun tftp 20000 u-boot.bin 119*4882a593Smuzhiyun protect off fe000000 fe0fffff 120*4882a593Smuzhiyun erase fe000000 fe0fffff 121*4882a593Smuzhiyun cp.b 20000 fe000000 xxxx 122*4882a593Smuzhiyun 123*4882a593SmuzhiyunYou have to supply the correct byte count with 'xxxx' from the TFTP result log. 124*4882a593SmuzhiyunMaybe 3ffff will work too, that corresponds to the erased sectors. 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun6. Notes 128*4882a593Smuzhiyun 1) The console baudrate for MPC832XEMDS is 115200bps. 129