1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) Freescale Semiconductor, Inc. 2006-2007 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Authors: Nick.Spence@freescale.com 5*4882a593Smuzhiyun * Wilson.Lo@freescale.com 6*4882a593Smuzhiyun * scottwood@freescale.com 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <common.h> 12*4882a593Smuzhiyun #include <mpc83xx.h> 13*4882a593Smuzhiyun #include <spd_sdram.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include <asm/bitops.h> 16*4882a593Smuzhiyun #include <asm/io.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #include <asm/processor.h> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC resume_from_sleep(void)23*4882a593Smuzhiyunstatic void resume_from_sleep(void) 24*4882a593Smuzhiyun { 25*4882a593Smuzhiyun u32 magic = *(u32 *)0; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun typedef void (*func_t)(void); 28*4882a593Smuzhiyun func_t resume = *(func_t *)4; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun if (magic == 0xf5153ae5) 31*4882a593Smuzhiyun resume(); 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun gd->flags &= ~GD_FLG_SILENT; 34*4882a593Smuzhiyun puts("\nResume from sleep failed: bad magic word\n"); 35*4882a593Smuzhiyun } 36*4882a593Smuzhiyun #endif 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* Fixed sdram init -- doesn't use serial presence detect. 39*4882a593Smuzhiyun * 40*4882a593Smuzhiyun * This is useful for faster booting in configs where the RAM is unlikely 41*4882a593Smuzhiyun * to be changed, or for things like NAND booting where space is tight. 42*4882a593Smuzhiyun */ fixed_sdram(void)43*4882a593Smuzhiyunstatic long fixed_sdram(void) 44*4882a593Smuzhiyun { 45*4882a593Smuzhiyun u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #ifndef CONFIG_SYS_RAMBOOT 48*4882a593Smuzhiyun volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; 49*4882a593Smuzhiyun u32 msize_log2 = __ilog2(msize); 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; 52*4882a593Smuzhiyun im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); 53*4882a593Smuzhiyun im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* 56*4882a593Smuzhiyun * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], 57*4882a593Smuzhiyun * or the DDR2 controller may fail to initialize correctly. 58*4882a593Smuzhiyun */ 59*4882a593Smuzhiyun __udelay(50000); 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) 62*4882a593Smuzhiyun #warning Chip select bounds is only configurable in 16MB increments 63*4882a593Smuzhiyun #endif 64*4882a593Smuzhiyun im->ddr.csbnds[0].csbnds = 65*4882a593Smuzhiyun ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | 66*4882a593Smuzhiyun (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & 67*4882a593Smuzhiyun CSBNDS_EA); 68*4882a593Smuzhiyun im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* Currently we use only one CS, so disable the other bank. */ 71*4882a593Smuzhiyun im->ddr.cs_config[1] = 0; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; 74*4882a593Smuzhiyun im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 75*4882a593Smuzhiyun im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 76*4882a593Smuzhiyun im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 77*4882a593Smuzhiyun im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC 80*4882a593Smuzhiyun if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) 81*4882a593Smuzhiyun im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI; 82*4882a593Smuzhiyun else 83*4882a593Smuzhiyun #endif 84*4882a593Smuzhiyun im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2; 87*4882a593Smuzhiyun im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; 88*4882a593Smuzhiyun im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; 91*4882a593Smuzhiyun sync(); 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* enable DDR controller */ 94*4882a593Smuzhiyun im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 95*4882a593Smuzhiyun #endif 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun return msize; 98*4882a593Smuzhiyun } 99*4882a593Smuzhiyun dram_init(void)100*4882a593Smuzhiyunint dram_init(void) 101*4882a593Smuzhiyun { 102*4882a593Smuzhiyun volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; 103*4882a593Smuzhiyun volatile fsl_lbc_t *lbc = &im->im_lbc; 104*4882a593Smuzhiyun u32 msize; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) 107*4882a593Smuzhiyun return -ENXIO; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* DDR SDRAM - Main SODIMM */ 110*4882a593Smuzhiyun msize = fixed_sdram(); 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* Local Bus setup lbcr and mrtpr */ 113*4882a593Smuzhiyun lbc->lbcr = CONFIG_SYS_LBC_LBCR; 114*4882a593Smuzhiyun lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; 115*4882a593Smuzhiyun sync(); 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC 118*4882a593Smuzhiyun if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) 119*4882a593Smuzhiyun resume_from_sleep(); 120*4882a593Smuzhiyun #endif 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun /* return total bus SDRAM size(bytes) -- DDR */ 123*4882a593Smuzhiyun gd->ram_size = msize; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun return 0; 126*4882a593Smuzhiyun } 127