1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Board-specific sbf ddr/sdram init. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <config.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun.global sbf_dram_init 12*4882a593Smuzhiyun.text 13*4882a593Smuzhiyun 14*4882a593Smuzhiyunsbf_dram_init: 15*4882a593Smuzhiyun /* Dram Initialization a1, a2, and d0 */ 16*4882a593Smuzhiyun /* mscr sdram */ 17*4882a593Smuzhiyun move.l #0xFC0A4074, %a1 18*4882a593Smuzhiyun move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1) 19*4882a593Smuzhiyun nop 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* SDRAM Chip 0 and 1 */ 22*4882a593Smuzhiyun move.l #0xFC0B8110, %a1 23*4882a593Smuzhiyun move.l #0xFC0B8114, %a2 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* calculate the size */ 26*4882a593Smuzhiyun move.l #0x13, %d1 27*4882a593Smuzhiyun move.l #(CONFIG_SYS_SDRAM_SIZE), %d2 28*4882a593Smuzhiyun#ifdef CONFIG_SYS_SDRAM_BASE1 29*4882a593Smuzhiyun lsr.l #1, %d2 30*4882a593Smuzhiyun#endif 31*4882a593Smuzhiyun 32*4882a593Smuzhiyundramsz_loop: 33*4882a593Smuzhiyun lsr.l #1, %d2 34*4882a593Smuzhiyun add.l #1, %d1 35*4882a593Smuzhiyun cmp.l #1, %d2 36*4882a593Smuzhiyun bne dramsz_loop 37*4882a593Smuzhiyun#ifdef CONFIG_SYS_NAND_BOOT 38*4882a593Smuzhiyun beq asm_nand_chk_status 39*4882a593Smuzhiyun#endif 40*4882a593Smuzhiyun /* SDRAM Chip 0 and 1 */ 41*4882a593Smuzhiyun move.l #(CONFIG_SYS_SDRAM_BASE), (%a1) 42*4882a593Smuzhiyun or.l %d1, (%a1) 43*4882a593Smuzhiyun#ifdef CONFIG_SYS_SDRAM_BASE1 44*4882a593Smuzhiyun move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2) 45*4882a593Smuzhiyun or.l %d1, (%a2) 46*4882a593Smuzhiyun#endif 47*4882a593Smuzhiyun nop 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* dram cfg1 and cfg2 */ 50*4882a593Smuzhiyun move.l #0xFC0B8008, %a1 51*4882a593Smuzhiyun move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1) 52*4882a593Smuzhiyun nop 53*4882a593Smuzhiyun move.l #0xFC0B800C, %a2 54*4882a593Smuzhiyun move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2) 55*4882a593Smuzhiyun nop 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun move.l #0xFC0B8000, %a1 /* Mode */ 58*4882a593Smuzhiyun move.l #0xFC0B8004, %a2 /* Ctrl */ 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* Issue PALL */ 61*4882a593Smuzhiyun move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2) 62*4882a593Smuzhiyun nop 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* Issue LEMR */ 65*4882a593Smuzhiyun move.l #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1) 66*4882a593Smuzhiyun nop 67*4882a593Smuzhiyun move.l #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1) 68*4882a593Smuzhiyun nop 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun move.l #1000, %d1 71*4882a593Smuzhiyun bsr asm_delay 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* Issue PALL */ 74*4882a593Smuzhiyun move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2) 75*4882a593Smuzhiyun nop 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* Perform two refresh cycles */ 78*4882a593Smuzhiyun move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0 79*4882a593Smuzhiyun nop 80*4882a593Smuzhiyun move.l %d0, (%a2) 81*4882a593Smuzhiyun move.l %d0, (%a2) 82*4882a593Smuzhiyun nop 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun move.l #(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1) 85*4882a593Smuzhiyun nop 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun move.l #500, %d1 88*4882a593Smuzhiyun bsr asm_delay 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun move.l #(CONFIG_SYS_SDRAM_CTRL), %d1 91*4882a593Smuzhiyun and.l #0x7FFFFFFF, %d1 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun or.l #0x10000C00, %d1 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun move.l %d1, (%a2) 96*4882a593Smuzhiyun nop 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun move.l #2000, %d1 99*4882a593Smuzhiyun bsr asm_delay 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun rts 102