1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2000-2003
3*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
6*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <common.h>
12*4882a593Smuzhiyun #include <spi.h>
13*4882a593Smuzhiyun #include <asm/immap.h>
14*4882a593Smuzhiyun #include <asm/io.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
17*4882a593Smuzhiyun
checkboard(void)18*4882a593Smuzhiyun int checkboard(void)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun /*
21*4882a593Smuzhiyun * need to to:
22*4882a593Smuzhiyun * Check serial flash size. if 2mb evb, else 8mb demo
23*4882a593Smuzhiyun */
24*4882a593Smuzhiyun puts("Board: ");
25*4882a593Smuzhiyun puts("Freescale M54451 EVB\n");
26*4882a593Smuzhiyun return 0;
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun
dram_init(void)29*4882a593Smuzhiyun int dram_init(void)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun u32 dramsize;
32*4882a593Smuzhiyun #ifdef CONFIG_CF_SBF
33*4882a593Smuzhiyun /*
34*4882a593Smuzhiyun * Serial Boot: The dram is already initialized in start.S
35*4882a593Smuzhiyun * only require to return DRAM size
36*4882a593Smuzhiyun */
37*4882a593Smuzhiyun dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
38*4882a593Smuzhiyun #else
39*4882a593Smuzhiyun sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
40*4882a593Smuzhiyun gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
41*4882a593Smuzhiyun u32 i;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun if ((in_be32(&sdram->sdcfg1) == CONFIG_SYS_SDRAM_CFG1) &&
46*4882a593Smuzhiyun (in_be32(&sdram->sdcfg2) == CONFIG_SYS_SDRAM_CFG2))
47*4882a593Smuzhiyun return dramsize;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun for (i = 0x13; i < 0x20; i++) {
50*4882a593Smuzhiyun if (dramsize == (1 << i))
51*4882a593Smuzhiyun break;
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun i--;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
60*4882a593Smuzhiyun out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun udelay(200);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /* Issue PALL */
65*4882a593Smuzhiyun out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
66*4882a593Smuzhiyun __asm__("nop");
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* Perform two refresh cycles */
69*4882a593Smuzhiyun out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
70*4882a593Smuzhiyun __asm__("nop");
71*4882a593Smuzhiyun out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
72*4882a593Smuzhiyun __asm__("nop");
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* Issue LEMR */
75*4882a593Smuzhiyun out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
76*4882a593Smuzhiyun __asm__("nop");
77*4882a593Smuzhiyun out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
78*4882a593Smuzhiyun __asm__("nop");
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun out_be32(&sdram->sdcr,
81*4882a593Smuzhiyun (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun udelay(100);
84*4882a593Smuzhiyun #endif
85*4882a593Smuzhiyun gd->ram_size = dramsize;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun return 0;
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun
testdram(void)90*4882a593Smuzhiyun int testdram(void)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun /* TODO: XXX XXX XXX */
93*4882a593Smuzhiyun printf("DRAM test not implemented!\n");
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun return (0);
96*4882a593Smuzhiyun }
97