1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2000-2003
3*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <config.h>
12*4882a593Smuzhiyun #include <common.h>
13*4882a593Smuzhiyun #include <asm/io.h>
14*4882a593Smuzhiyun #include <asm/immap.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #if defined(CONFIG_CMD_NAND)
19*4882a593Smuzhiyun #include <nand.h>
20*4882a593Smuzhiyun #include <linux/mtd/mtd.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define SET_CLE 0x10
23*4882a593Smuzhiyun #define SET_ALE 0x08
24*4882a593Smuzhiyun
nand_hwcontrol(struct mtd_info * mtdinfo,int cmd,unsigned int ctrl)25*4882a593Smuzhiyun static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun struct nand_chip *this = mtd_to_nand(mtdinfo);
28*4882a593Smuzhiyun volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun if (ctrl & NAND_CTRL_CHANGE) {
31*4882a593Smuzhiyun ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun IO_ADDR_W &= ~(SET_ALE | SET_CLE);
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun if (ctrl & NAND_NCE)
36*4882a593Smuzhiyun *nCE &= 0xFFFB;
37*4882a593Smuzhiyun else
38*4882a593Smuzhiyun *nCE |= 0x0004;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun if (ctrl & NAND_CLE)
41*4882a593Smuzhiyun IO_ADDR_W |= SET_CLE;
42*4882a593Smuzhiyun if (ctrl & NAND_ALE)
43*4882a593Smuzhiyun IO_ADDR_W |= SET_ALE;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun this->IO_ADDR_W = (void *)IO_ADDR_W;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun if (cmd != NAND_CMD_NONE)
50*4882a593Smuzhiyun writeb(cmd, this->IO_ADDR_W);
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
board_nand_init(struct nand_chip * nand)53*4882a593Smuzhiyun int board_nand_init(struct nand_chip *nand)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun gpio_t *gpio = (gpio_t *) MMAP_GPIO;
56*4882a593Smuzhiyun fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun clrbits_be32(&fbcs->csmr2, FBCS_CSMR_WP);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /*
61*4882a593Smuzhiyun * set up pin configuration - enabled 2nd output buffer's signals
62*4882a593Smuzhiyun * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
63*4882a593Smuzhiyun * to use nCE signal
64*4882a593Smuzhiyun */
65*4882a593Smuzhiyun clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3);
66*4882a593Smuzhiyun setbits_8(&gpio->pddr_timer, 0x08);
67*4882a593Smuzhiyun setbits_8(&gpio->ppd_timer, 0x08);
68*4882a593Smuzhiyun out_8(&gpio->pclrr_timer, 0);
69*4882a593Smuzhiyun out_8(&gpio->podr_timer, 0);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun nand->chip_delay = 60;
72*4882a593Smuzhiyun nand->ecc.mode = NAND_ECC_SOFT;
73*4882a593Smuzhiyun nand->cmd_ctrl = nand_hwcontrol;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun return 0;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun #endif
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