1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2000-2003 3*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <common.h> 9*4882a593Smuzhiyun #include <asm/immap.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 12*4882a593Smuzhiyun checkboard(void)13*4882a593Smuzhiyunint checkboard (void) 14*4882a593Smuzhiyun { 15*4882a593Smuzhiyun puts ("Board: Freescale M5282EVB Evaluation Board\n"); 16*4882a593Smuzhiyun return 0; 17*4882a593Smuzhiyun } 18*4882a593Smuzhiyun dram_init(void)19*4882a593Smuzhiyunint dram_init(void) 20*4882a593Smuzhiyun { 21*4882a593Smuzhiyun u32 dramsize, i, dramclk; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; 24*4882a593Smuzhiyun for (i = 0x13; i < 0x20; i++) { 25*4882a593Smuzhiyun if (dramsize == (1 << i)) 26*4882a593Smuzhiyun break; 27*4882a593Smuzhiyun } 28*4882a593Smuzhiyun i--; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE)) 31*4882a593Smuzhiyun { 32*4882a593Smuzhiyun dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ); 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* Initialize DRAM Control Register: DCR */ 35*4882a593Smuzhiyun MCFSDRAMC_DCR = (0 36*4882a593Smuzhiyun | MCFSDRAMC_DCR_RTIM_6 37*4882a593Smuzhiyun | MCFSDRAMC_DCR_RC((15 * dramclk)>>4)); 38*4882a593Smuzhiyun asm("nop"); 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* Initialize DACR0 */ 41*4882a593Smuzhiyun MCFSDRAMC_DACR0 = (0 42*4882a593Smuzhiyun | MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE) 43*4882a593Smuzhiyun | MCFSDRAMC_DACR_CASL(1) 44*4882a593Smuzhiyun | MCFSDRAMC_DACR_CBM(3) 45*4882a593Smuzhiyun | MCFSDRAMC_DACR_PS_32); 46*4882a593Smuzhiyun asm("nop"); 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* Initialize DMR0 */ 49*4882a593Smuzhiyun MCFSDRAMC_DMR0 = (0 50*4882a593Smuzhiyun | ((dramsize - 1) & 0xFFFC0000) 51*4882a593Smuzhiyun | MCFSDRAMC_DMR_V); 52*4882a593Smuzhiyun asm("nop"); 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* Set IP (bit 3) in DACR */ 55*4882a593Smuzhiyun MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP; 56*4882a593Smuzhiyun asm("nop"); 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* Wait 30ns to allow banks to precharge */ 59*4882a593Smuzhiyun for (i = 0; i < 5; i++) { 60*4882a593Smuzhiyun asm ("nop"); 61*4882a593Smuzhiyun } 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* Write to this block to initiate precharge */ 64*4882a593Smuzhiyun *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xA5A59696; 65*4882a593Smuzhiyun asm("nop"); 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* Set RE (bit 15) in DACR */ 68*4882a593Smuzhiyun MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE; 69*4882a593Smuzhiyun asm("nop"); 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* Wait for at least 8 auto refresh cycles to occur */ 72*4882a593Smuzhiyun for (i = 0; i < 2000; i++) { 73*4882a593Smuzhiyun asm(" nop"); 74*4882a593Smuzhiyun } 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* Finish the configuration by issuing the IMRS. */ 77*4882a593Smuzhiyun MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS; 78*4882a593Smuzhiyun asm("nop"); 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* Write to the SDRAM Mode Register */ 81*4882a593Smuzhiyun *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696; 82*4882a593Smuzhiyun } 83*4882a593Smuzhiyun gd->ram_size = dramsize; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun return 0; 86*4882a593Smuzhiyun } 87