1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2000-2003
3*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6*4882a593Smuzhiyun * Hayden Fraser (Hayden.Fraser@freescale.com)
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <common.h>
12*4882a593Smuzhiyun #include <asm/immap.h>
13*4882a593Smuzhiyun #include <netdev.h>
14*4882a593Smuzhiyun #include <asm/io.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
17*4882a593Smuzhiyun
checkboard(void)18*4882a593Smuzhiyun int checkboard(void)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun puts("Board: ");
21*4882a593Smuzhiyun puts("Freescale MCF5253 DEMO\n");
22*4882a593Smuzhiyun return 0;
23*4882a593Smuzhiyun };
24*4882a593Smuzhiyun
dram_init(void)25*4882a593Smuzhiyun int dram_init(void)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun u32 dramsize = 0;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /*
30*4882a593Smuzhiyun * Check to see if the SDRAM has already been initialized
31*4882a593Smuzhiyun * by a run control tool
32*4882a593Smuzhiyun */
33*4882a593Smuzhiyun if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
34*4882a593Smuzhiyun u32 RC, temp;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun RC = (CONFIG_SYS_CLK / 1000000) >> 1;
37*4882a593Smuzhiyun RC = (RC * 15) >> 4;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* Initialize DRAM Control Register: DCR */
40*4882a593Smuzhiyun mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
41*4882a593Smuzhiyun __asm__("nop");
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun mbar_writeLong(MCFSIM_DACR0, 0x00003224);
44*4882a593Smuzhiyun __asm__("nop");
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* Initialize DMR0 */
47*4882a593Smuzhiyun dramsize = (CONFIG_SYS_SDRAM_SIZE << 20);
48*4882a593Smuzhiyun temp = (dramsize - 1) & 0xFFFC0000;
49*4882a593Smuzhiyun mbar_writeLong(MCFSIM_DMR0, temp | 1);
50*4882a593Smuzhiyun __asm__("nop");
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun mbar_writeLong(MCFSIM_DACR0, 0x0000322c);
53*4882a593Smuzhiyun mb();
54*4882a593Smuzhiyun __asm__("nop");
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /* Write to this block to initiate precharge */
57*4882a593Smuzhiyun *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
58*4882a593Smuzhiyun mb();
59*4882a593Smuzhiyun __asm__("nop");
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* Set RE bit in DACR */
62*4882a593Smuzhiyun mbar_writeLong(MCFSIM_DACR0,
63*4882a593Smuzhiyun mbar_readLong(MCFSIM_DACR0) | 0x8000);
64*4882a593Smuzhiyun __asm__("nop");
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* Wait for at least 8 auto refresh cycles to occur */
67*4882a593Smuzhiyun udelay(500);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /* Finish the configuration by issuing the MRS */
70*4882a593Smuzhiyun mbar_writeLong(MCFSIM_DACR0,
71*4882a593Smuzhiyun mbar_readLong(MCFSIM_DACR0) | 0x0040);
72*4882a593Smuzhiyun __asm__("nop");
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
75*4882a593Smuzhiyun mb();
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun gd->ram_size = dramsize;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun return 0;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
testdram(void)83*4882a593Smuzhiyun int testdram(void)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun /* TODO: XXX XXX XXX */
86*4882a593Smuzhiyun printf("DRAM test not implemented!\n");
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun return (0);
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun #ifdef CONFIG_IDE
92*4882a593Smuzhiyun #include <ata.h>
ide_preinit(void)93*4882a593Smuzhiyun int ide_preinit(void)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun return (0);
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
ide_set_reset(int idereset)98*4882a593Smuzhiyun void ide_set_reset(int idereset)
99*4882a593Smuzhiyun {
100*4882a593Smuzhiyun atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
101*4882a593Smuzhiyun long period;
102*4882a593Smuzhiyun /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
103*4882a593Smuzhiyun int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
104*4882a593Smuzhiyun {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
105*4882a593Smuzhiyun {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
106*4882a593Smuzhiyun {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
107*4882a593Smuzhiyun {25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */
108*4882a593Smuzhiyun };
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun if (idereset) {
111*4882a593Smuzhiyun /* control reset */
112*4882a593Smuzhiyun out_8(&ata->cr, 0);
113*4882a593Smuzhiyun udelay(100);
114*4882a593Smuzhiyun } else {
115*4882a593Smuzhiyun mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun #define CALC_TIMING(t) (t + period - 1) / period
118*4882a593Smuzhiyun period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun /*ata->ton = CALC_TIMING (180); */
121*4882a593Smuzhiyun out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
122*4882a593Smuzhiyun out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
123*4882a593Smuzhiyun out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
124*4882a593Smuzhiyun out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
125*4882a593Smuzhiyun out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
126*4882a593Smuzhiyun out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
127*4882a593Smuzhiyun out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun /* IORDY enable */
130*4882a593Smuzhiyun out_8(&ata->cr, 0x40);
131*4882a593Smuzhiyun udelay(2000);
132*4882a593Smuzhiyun /* IORDY enable */
133*4882a593Smuzhiyun setbits_8(&ata->cr, 0x01);
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun #endif /* CONFIG_IDE */
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun #ifdef CONFIG_DRIVER_DM9000
board_eth_init(bd_t * bis)140*4882a593Smuzhiyun int board_eth_init(bd_t *bis)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun return dm9000_initialize(bis);
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun #endif
145