1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2000-2003
3*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <config.h>
12*4882a593Smuzhiyun #include <common.h>
13*4882a593Smuzhiyun #include <asm/immap.h>
14*4882a593Smuzhiyun #include <asm/io.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
17*4882a593Smuzhiyun
checkboard(void)18*4882a593Smuzhiyun int checkboard(void)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun puts("Board: ");
21*4882a593Smuzhiyun puts("Freescale M5235 EVB\n");
22*4882a593Smuzhiyun return 0;
23*4882a593Smuzhiyun };
24*4882a593Smuzhiyun
dram_init(void)25*4882a593Smuzhiyun int dram_init(void)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
28*4882a593Smuzhiyun gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
29*4882a593Smuzhiyun u32 dramsize, i, dramclk;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /*
32*4882a593Smuzhiyun * When booting from external Flash, the port-size is less than
33*4882a593Smuzhiyun * the port-size of SDRAM. In this case it is necessary to enable
34*4882a593Smuzhiyun * Data[15:0] on Port Address/Data.
35*4882a593Smuzhiyun */
36*4882a593Smuzhiyun out_8(&gpio->par_ad,
37*4882a593Smuzhiyun GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 |
38*4882a593Smuzhiyun GPIO_PAR_AD_DATAL);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /* Initialize PAR to enable SDRAM signals */
41*4882a593Smuzhiyun out_8(&gpio->par_sdram,
42*4882a593Smuzhiyun GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS |
43*4882a593Smuzhiyun GPIO_PAR_SDRAM_SRAS | GPIO_PAR_SDRAM_SCKE |
44*4882a593Smuzhiyun GPIO_PAR_SDRAM_SDCS(3));
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
47*4882a593Smuzhiyun for (i = 0x13; i < 0x20; i++) {
48*4882a593Smuzhiyun if (dramsize == (1 << i))
49*4882a593Smuzhiyun break;
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun i--;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun if (!(in_be32(&sdram->dacr0) & SDRAMC_DARCn_RE)) {
54*4882a593Smuzhiyun dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /* Initialize DRAM Control Register: DCR */
57*4882a593Smuzhiyun out_be16(&sdram->dcr, SDRAMC_DCR_RTIM_9CLKS |
58*4882a593Smuzhiyun SDRAMC_DCR_RTIM_6CLKS |
59*4882a593Smuzhiyun SDRAMC_DCR_RC((15 * dramclk) >> 4));
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* Initialize DACR0 */
62*4882a593Smuzhiyun out_be32(&sdram->dacr0,
63*4882a593Smuzhiyun SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) |
64*4882a593Smuzhiyun SDRAMC_DARCn_CASL_C1 | SDRAMC_DARCn_CBM_CMD20 |
65*4882a593Smuzhiyun SDRAMC_DARCn_PS_32);
66*4882a593Smuzhiyun asm("nop");
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* Initialize DMR0 */
69*4882a593Smuzhiyun out_be32(&sdram->dmr0,
70*4882a593Smuzhiyun ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V);
71*4882a593Smuzhiyun asm("nop");
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /* Set IP (bit 3) in DACR */
74*4882a593Smuzhiyun setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IP);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /* Wait 30ns to allow banks to precharge */
77*4882a593Smuzhiyun for (i = 0; i < 5; i++) {
78*4882a593Smuzhiyun asm("nop");
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /* Write to this block to initiate precharge */
82*4882a593Smuzhiyun *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* Set RE (bit 15) in DACR */
85*4882a593Smuzhiyun setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* Wait for at least 8 auto refresh cycles to occur */
88*4882a593Smuzhiyun for (i = 0; i < 0x2000; i++) {
89*4882a593Smuzhiyun asm("nop");
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun /* Finish the configuration by issuing the MRS. */
93*4882a593Smuzhiyun setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IMRS);
94*4882a593Smuzhiyun asm("nop");
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun /* Write to the SDRAM Mode Register */
97*4882a593Smuzhiyun *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun gd->ram_size = dramsize;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun return 0;
103*4882a593Smuzhiyun };
104*4882a593Smuzhiyun
testdram(void)105*4882a593Smuzhiyun int testdram(void)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun /* TODO: XXX XXX XXX */
108*4882a593Smuzhiyun printf("DRAM test not implemented!\n");
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun return (0);
111*4882a593Smuzhiyun }
112