1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2000-2003
3*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <common.h>
12*4882a593Smuzhiyun #include <asm/immap.h>
13*4882a593Smuzhiyun #include <asm/io.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
16*4882a593Smuzhiyun
checkboard(void)17*4882a593Smuzhiyun int checkboard(void)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun puts("Board: ");
20*4882a593Smuzhiyun puts("Freescale M52277 EVB\n");
21*4882a593Smuzhiyun return 0;
22*4882a593Smuzhiyun };
23*4882a593Smuzhiyun
dram_init(void)24*4882a593Smuzhiyun int dram_init(void)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun u32 dramsize;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #ifdef CONFIG_CF_SBF
29*4882a593Smuzhiyun /*
30*4882a593Smuzhiyun * Serial Boot: The dram is already initialized in start.S
31*4882a593Smuzhiyun * only require to return DRAM size
32*4882a593Smuzhiyun */
33*4882a593Smuzhiyun dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
34*4882a593Smuzhiyun #else
35*4882a593Smuzhiyun sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
36*4882a593Smuzhiyun gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
37*4882a593Smuzhiyun u32 i;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun for (i = 0x13; i < 0x20; i++) {
42*4882a593Smuzhiyun if (dramsize == (1 << i))
43*4882a593Smuzhiyun break;
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun i--;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
52*4882a593Smuzhiyun out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /* Issue PALL */
55*4882a593Smuzhiyun out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
56*4882a593Smuzhiyun __asm__("nop");
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* Issue LEMR */
59*4882a593Smuzhiyun out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
60*4882a593Smuzhiyun __asm__("nop");
61*4882a593Smuzhiyun out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD);
62*4882a593Smuzhiyun __asm__("nop");
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun udelay(1000);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* Issue PALL */
67*4882a593Smuzhiyun out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
68*4882a593Smuzhiyun __asm__("nop");
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /* Perform two refresh cycles */
71*4882a593Smuzhiyun out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
72*4882a593Smuzhiyun __asm__("nop");
73*4882a593Smuzhiyun out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
74*4882a593Smuzhiyun __asm__("nop");
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun out_be32(&sdram->sdcr,
77*4882a593Smuzhiyun (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun udelay(100);
80*4882a593Smuzhiyun #endif
81*4882a593Smuzhiyun gd->ram_size = dramsize;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun return 0;
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun
testdram(void)86*4882a593Smuzhiyun int testdram(void)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun /* TODO: XXX XXX XXX */
89*4882a593Smuzhiyun printf("DRAM test not implemented!\n");
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun return (0);
92*4882a593Smuzhiyun }
93