1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2015 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <command.h>
10*4882a593Smuzhiyun #include <netdev.h>
11*4882a593Smuzhiyun #include <malloc.h>
12*4882a593Smuzhiyun #include <fsl_mdio.h>
13*4882a593Smuzhiyun #include <miiphy.h>
14*4882a593Smuzhiyun #include <phy.h>
15*4882a593Smuzhiyun #include <fm_eth.h>
16*4882a593Smuzhiyun #include <asm/io.h>
17*4882a593Smuzhiyun #include <exports.h>
18*4882a593Smuzhiyun #include <asm/arch/fsl_serdes.h>
19*4882a593Smuzhiyun #include <fsl-mc/fsl_mc.h>
20*4882a593Smuzhiyun #include <fsl-mc/ldpaa_wriop.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
23*4882a593Smuzhiyun
board_eth_init(bd_t * bis)24*4882a593Smuzhiyun int board_eth_init(bd_t *bis)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun #if defined(CONFIG_FSL_MC_ENET)
27*4882a593Smuzhiyun int i, interface;
28*4882a593Smuzhiyun struct memac_mdio_info mdio_info;
29*4882a593Smuzhiyun struct mii_dev *dev;
30*4882a593Smuzhiyun struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
31*4882a593Smuzhiyun u32 srds_s1;
32*4882a593Smuzhiyun struct memac_mdio_controller *reg;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun srds_s1 = in_le32(&gur->rcwsr[28]) &
35*4882a593Smuzhiyun FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
36*4882a593Smuzhiyun srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
39*4882a593Smuzhiyun mdio_info.regs = reg;
40*4882a593Smuzhiyun mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /* Register the EMI 1 */
43*4882a593Smuzhiyun fm_memac_mdio_init(bis, &mdio_info);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
46*4882a593Smuzhiyun mdio_info.regs = reg;
47*4882a593Smuzhiyun mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* Register the EMI 2 */
50*4882a593Smuzhiyun fm_memac_mdio_init(bis, &mdio_info);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun switch (srds_s1) {
53*4882a593Smuzhiyun case 0x2A:
54*4882a593Smuzhiyun wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
55*4882a593Smuzhiyun wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
56*4882a593Smuzhiyun wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
57*4882a593Smuzhiyun wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
58*4882a593Smuzhiyun wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1);
59*4882a593Smuzhiyun wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2);
60*4882a593Smuzhiyun wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3);
61*4882a593Smuzhiyun wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun break;
64*4882a593Smuzhiyun case 0x4B:
65*4882a593Smuzhiyun wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
66*4882a593Smuzhiyun wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
67*4882a593Smuzhiyun wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
68*4882a593Smuzhiyun wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun break;
71*4882a593Smuzhiyun default:
72*4882a593Smuzhiyun printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n",
73*4882a593Smuzhiyun srds_s1);
74*4882a593Smuzhiyun break;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) {
78*4882a593Smuzhiyun interface = wriop_get_enet_if(i);
79*4882a593Smuzhiyun switch (interface) {
80*4882a593Smuzhiyun case PHY_INTERFACE_MODE_XGMII:
81*4882a593Smuzhiyun dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
82*4882a593Smuzhiyun wriop_set_mdio(i, dev);
83*4882a593Smuzhiyun break;
84*4882a593Smuzhiyun default:
85*4882a593Smuzhiyun break;
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) {
90*4882a593Smuzhiyun switch (wriop_get_enet_if(i)) {
91*4882a593Smuzhiyun case PHY_INTERFACE_MODE_XGMII:
92*4882a593Smuzhiyun dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
93*4882a593Smuzhiyun wriop_set_mdio(i, dev);
94*4882a593Smuzhiyun break;
95*4882a593Smuzhiyun default:
96*4882a593Smuzhiyun break;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun cpu_eth_init(bis);
101*4882a593Smuzhiyun #endif /* CONFIG_FSL_MC_ENET */
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun #ifdef CONFIG_PHY_AQUANTIA
104*4882a593Smuzhiyun /*
105*4882a593Smuzhiyun * Export functions to be used by AQ firmware
106*4882a593Smuzhiyun * upload application
107*4882a593Smuzhiyun */
108*4882a593Smuzhiyun gd->jt->strcpy = strcpy;
109*4882a593Smuzhiyun gd->jt->mdelay = mdelay;
110*4882a593Smuzhiyun gd->jt->mdio_get_current_dev = mdio_get_current_dev;
111*4882a593Smuzhiyun gd->jt->phy_find_by_mask = phy_find_by_mask;
112*4882a593Smuzhiyun gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
113*4882a593Smuzhiyun gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
114*4882a593Smuzhiyun #endif
115*4882a593Smuzhiyun return pci_eth_init(bis);
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun #if defined(CONFIG_RESET_PHY_R)
reset_phy(void)119*4882a593Smuzhiyun void reset_phy(void)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun mc_env_boot();
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun #endif /* CONFIG_RESET_PHY_R */
124