1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2015 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __DDR_H__ 8*4882a593Smuzhiyun #define __DDR_H__ 9*4882a593Smuzhiyun struct board_specific_parameters { 10*4882a593Smuzhiyun u32 n_ranks; 11*4882a593Smuzhiyun u32 datarate_mhz_high; 12*4882a593Smuzhiyun u32 rank_gb; 13*4882a593Smuzhiyun u32 clk_adjust; 14*4882a593Smuzhiyun u32 wrlvl_start; 15*4882a593Smuzhiyun u32 wrlvl_ctl_2; 16*4882a593Smuzhiyun u32 wrlvl_ctl_3; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* 20*4882a593Smuzhiyun * These tables contain all valid speeds we want to override with board 21*4882a593Smuzhiyun * specific parameters. datarate_mhz_high values need to be in ascending order 22*4882a593Smuzhiyun * for each n_ranks group. 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun static const struct board_specific_parameters udimm0[] = { 26*4882a593Smuzhiyun /* 27*4882a593Smuzhiyun * memory controller 0 28*4882a593Smuzhiyun * num| hi| rank| clk| wrlvl | wrlvl | wrlvl 29*4882a593Smuzhiyun * ranks| mhz| GB |adjst| start | ctl2 | ctl3 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, 32*4882a593Smuzhiyun {2, 1666, 0, 10, 9, 0x090A0B0E, 0x0F11110C,}, 33*4882a593Smuzhiyun {2, 1900, 0, 12, 0xA, 0x0B0C0E11, 0x1214140F,}, 34*4882a593Smuzhiyun {2, 2300, 0, 12, 0xB, 0x0C0D0F12, 0x14161610,}, 35*4882a593Smuzhiyun {} 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* DP-DDR DIMM */ 39*4882a593Smuzhiyun static const struct board_specific_parameters udimm2[] = { 40*4882a593Smuzhiyun /* 41*4882a593Smuzhiyun * memory controller 2 42*4882a593Smuzhiyun * num| hi| rank| clk| wrlvl | wrlvl | wrlvl 43*4882a593Smuzhiyun * ranks| mhz| GB |adjst| start | ctl2 | ctl3 44*4882a593Smuzhiyun */ 45*4882a593Smuzhiyun {2, 1350, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,}, 46*4882a593Smuzhiyun {2, 1666, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,}, 47*4882a593Smuzhiyun {2, 1900, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,}, 48*4882a593Smuzhiyun {2, 2200, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,}, 49*4882a593Smuzhiyun {} 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun static const struct board_specific_parameters rdimm0[] = { 53*4882a593Smuzhiyun /* 54*4882a593Smuzhiyun * memory controller 0 55*4882a593Smuzhiyun * num| hi| rank| clk| wrlvl | wrlvl | wrlvl 56*4882a593Smuzhiyun * ranks| mhz| GB |adjst| start | ctl2 | ctl3 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, 59*4882a593Smuzhiyun {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,}, 60*4882a593Smuzhiyun {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, 61*4882a593Smuzhiyun {2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,}, 62*4882a593Smuzhiyun {} 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* DP-DDR DIMM */ 66*4882a593Smuzhiyun static const struct board_specific_parameters rdimm2[] = { 67*4882a593Smuzhiyun /* 68*4882a593Smuzhiyun * memory controller 2 69*4882a593Smuzhiyun * num| hi| rank| clk| wrlvl | wrlvl | wrlvl 70*4882a593Smuzhiyun * ranks| mhz| GB |adjst| start | ctl2 | ctl3 71*4882a593Smuzhiyun */ 72*4882a593Smuzhiyun {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, 73*4882a593Smuzhiyun {2, 1666, 0, 8, 7, 0x0B0A090C, 0x0D0F100B,}, 74*4882a593Smuzhiyun {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, 75*4882a593Smuzhiyun {2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,}, 76*4882a593Smuzhiyun {} 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun static const struct board_specific_parameters *udimms[] = { 80*4882a593Smuzhiyun udimm0, 81*4882a593Smuzhiyun udimm0, 82*4882a593Smuzhiyun udimm2, 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun static const struct board_specific_parameters *rdimms[] = { 86*4882a593Smuzhiyun rdimm0, 87*4882a593Smuzhiyun rdimm0, 88*4882a593Smuzhiyun rdimm2, 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #endif 93