1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2014 Freescale Semiconductor
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun #include <common.h>
7*4882a593Smuzhiyun #include <malloc.h>
8*4882a593Smuzhiyun #include <errno.h>
9*4882a593Smuzhiyun #include <netdev.h>
10*4882a593Smuzhiyun #include <fsl_ifc.h>
11*4882a593Smuzhiyun #include <fsl_ddr.h>
12*4882a593Smuzhiyun #include <asm/io.h>
13*4882a593Smuzhiyun #include <fdt_support.h>
14*4882a593Smuzhiyun #include <linux/libfdt.h>
15*4882a593Smuzhiyun #include <fsl-mc/fsl_mc.h>
16*4882a593Smuzhiyun #include <environment.h>
17*4882a593Smuzhiyun #include <asm/arch/soc.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
20*4882a593Smuzhiyun
board_init(void)21*4882a593Smuzhiyun int board_init(void)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun init_final_memctl_regs();
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #ifdef CONFIG_ENV_IS_NOWHERE
26*4882a593Smuzhiyun gd->env_addr = (ulong)&default_environment[0];
27*4882a593Smuzhiyun #endif
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun return 0;
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun
board_early_init_f(void)32*4882a593Smuzhiyun int board_early_init_f(void)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun fsl_lsch3_early_init_f();
35*4882a593Smuzhiyun return 0;
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
detail_board_ddr_info(void)38*4882a593Smuzhiyun void detail_board_ddr_info(void)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun puts("\nDDR ");
41*4882a593Smuzhiyun print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
42*4882a593Smuzhiyun print_ddr_info(0);
43*4882a593Smuzhiyun #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
44*4882a593Smuzhiyun if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
45*4882a593Smuzhiyun puts("\nDP-DDR ");
46*4882a593Smuzhiyun print_size(gd->bd->bi_dram[2].size, "");
47*4882a593Smuzhiyun print_ddr_info(CONFIG_DP_DDR_CTRL);
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun #endif
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun #if defined(CONFIG_ARCH_MISC_INIT)
arch_misc_init(void)53*4882a593Smuzhiyun int arch_misc_init(void)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun return 0;
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun #endif
58*4882a593Smuzhiyun
board_eth_init(bd_t * bis)59*4882a593Smuzhiyun int board_eth_init(bd_t *bis)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun int error = 0;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun #ifdef CONFIG_SMC91111
64*4882a593Smuzhiyun error = smc91111_initialize(0, CONFIG_SMC91111_BASE);
65*4882a593Smuzhiyun #endif
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
68*4882a593Smuzhiyun error = cpu_eth_init(bis);
69*4882a593Smuzhiyun #endif
70*4882a593Smuzhiyun return error;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
fdt_fixup_board_enet(void * fdt)74*4882a593Smuzhiyun void fdt_fixup_board_enet(void *fdt)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun int offset;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun offset = fdt_path_offset(fdt, "/soc/fsl-mc");
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun /*
81*4882a593Smuzhiyun * TODO: Remove this when backward compatibility
82*4882a593Smuzhiyun * with old DT node (/fsl-mc) is no longer needed.
83*4882a593Smuzhiyun */
84*4882a593Smuzhiyun if (offset < 0)
85*4882a593Smuzhiyun offset = fdt_path_offset(fdt, "/fsl-mc");
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun if (offset < 0) {
88*4882a593Smuzhiyun printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
89*4882a593Smuzhiyun __func__, offset);
90*4882a593Smuzhiyun return;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun if (get_mc_boot_status() == 0)
94*4882a593Smuzhiyun fdt_status_okay(fdt, offset);
95*4882a593Smuzhiyun else
96*4882a593Smuzhiyun fdt_status_fail(fdt, offset);
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
board_quiesce_devices(void)99*4882a593Smuzhiyun void board_quiesce_devices(void)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun fsl_mc_ldpaa_exit(gd->bd);
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun #endif
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun #ifdef CONFIG_OF_BOARD_SETUP
ft_board_setup(void * blob,bd_t * bd)106*4882a593Smuzhiyun int ft_board_setup(void *blob, bd_t *bd)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun u64 base[CONFIG_NR_DRAM_BANKS];
109*4882a593Smuzhiyun u64 size[CONFIG_NR_DRAM_BANKS];
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun ft_cpu_setup(blob, bd);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun /* fixup DT for the two GPP DDR banks */
114*4882a593Smuzhiyun base[0] = gd->bd->bi_dram[0].start;
115*4882a593Smuzhiyun size[0] = gd->bd->bi_dram[0].size;
116*4882a593Smuzhiyun base[1] = gd->bd->bi_dram[1].start;
117*4882a593Smuzhiyun size[1] = gd->bd->bi_dram[1].size;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun #ifdef CONFIG_RESV_RAM
120*4882a593Smuzhiyun /* reduce size if reserved memory is within this bank */
121*4882a593Smuzhiyun if (gd->arch.resv_ram >= base[0] &&
122*4882a593Smuzhiyun gd->arch.resv_ram < base[0] + size[0])
123*4882a593Smuzhiyun size[0] = gd->arch.resv_ram - base[0];
124*4882a593Smuzhiyun else if (gd->arch.resv_ram >= base[1] &&
125*4882a593Smuzhiyun gd->arch.resv_ram < base[1] + size[1])
126*4882a593Smuzhiyun size[1] = gd->arch.resv_ram - base[1];
127*4882a593Smuzhiyun #endif
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun fdt_fixup_memory_banks(blob, base, size, 2);
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
132*4882a593Smuzhiyun fdt_fixup_board_enet(blob);
133*4882a593Smuzhiyun #endif
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun return 0;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun #endif
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun #if defined(CONFIG_RESET_PHY_R)
reset_phy(void)140*4882a593Smuzhiyun void reset_phy(void)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun #endif
144