1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2014 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __DDR_H__ 8*4882a593Smuzhiyun #define __DDR_H__ 9*4882a593Smuzhiyun struct board_specific_parameters { 10*4882a593Smuzhiyun u32 n_ranks; 11*4882a593Smuzhiyun u32 datarate_mhz_high; 12*4882a593Smuzhiyun u32 rank_gb; 13*4882a593Smuzhiyun u32 clk_adjust; 14*4882a593Smuzhiyun u32 wrlvl_start; 15*4882a593Smuzhiyun u32 wrlvl_ctl_2; 16*4882a593Smuzhiyun u32 wrlvl_ctl_3; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* 20*4882a593Smuzhiyun * These tables contain all valid speeds we want to override with board 21*4882a593Smuzhiyun * specific parameters. datarate_mhz_high values need to be in ascending order 22*4882a593Smuzhiyun * for each n_ranks group. 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun static const struct board_specific_parameters udimm0[] = { 26*4882a593Smuzhiyun /* 27*4882a593Smuzhiyun * memory controller 0 28*4882a593Smuzhiyun * num| hi| rank| clk| wrlvl | wrlvl | wrlvl 29*4882a593Smuzhiyun * ranks| mhz| GB |adjst| start | ctl2 | ctl3 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun {2, 2140, 0, 4, 4, 0x0, 0x0}, 32*4882a593Smuzhiyun {1, 2140, 0, 4, 4, 0x0, 0x0}, 33*4882a593Smuzhiyun {} 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* DP-DDR DIMM */ 37*4882a593Smuzhiyun static const struct board_specific_parameters udimm2[] = { 38*4882a593Smuzhiyun /* 39*4882a593Smuzhiyun * memory controller 2 40*4882a593Smuzhiyun * num| hi| rank| clk| wrlvl | wrlvl | wrlvl 41*4882a593Smuzhiyun * ranks| mhz| GB |adjst| start | ctl2 | ctl3 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun {2, 2140, 0, 4, 4, 0x0, 0x0}, 44*4882a593Smuzhiyun {1, 2140, 0, 4, 4, 0x0, 0x0}, 45*4882a593Smuzhiyun {} 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun static const struct board_specific_parameters rdimm0[] = { 49*4882a593Smuzhiyun /* 50*4882a593Smuzhiyun * memory controller 0 51*4882a593Smuzhiyun * num| hi| rank| clk| wrlvl | wrlvl | wrlvl 52*4882a593Smuzhiyun * ranks| mhz| GB |adjst| start | ctl2 | ctl3 53*4882a593Smuzhiyun */ 54*4882a593Smuzhiyun {4, 2140, 0, 5, 4, 0x0, 0x0}, 55*4882a593Smuzhiyun {2, 2140, 0, 5, 4, 0x0, 0x0}, 56*4882a593Smuzhiyun {1, 2140, 0, 4, 4, 0x0, 0x0}, 57*4882a593Smuzhiyun {} 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* DP-DDR DIMM */ 61*4882a593Smuzhiyun static const struct board_specific_parameters rdimm2[] = { 62*4882a593Smuzhiyun /* 63*4882a593Smuzhiyun * memory controller 2 64*4882a593Smuzhiyun * num| hi| rank| clk| wrlvl | wrlvl | wrlvl 65*4882a593Smuzhiyun * ranks| mhz| GB |adjst| start | ctl2 | ctl3 66*4882a593Smuzhiyun */ 67*4882a593Smuzhiyun {4, 2140, 0, 5, 4, 0x0, 0x0}, 68*4882a593Smuzhiyun {2, 2140, 0, 5, 4, 0x0, 0x0}, 69*4882a593Smuzhiyun {1, 2140, 0, 4, 4, 0x0, 0x0}, 70*4882a593Smuzhiyun {} 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun static const struct board_specific_parameters *udimms[] = { 74*4882a593Smuzhiyun udimm0, 75*4882a593Smuzhiyun udimm0, 76*4882a593Smuzhiyun udimm2, 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun static const struct board_specific_parameters *rdimms[] = { 80*4882a593Smuzhiyun rdimm0, 81*4882a593Smuzhiyun rdimm0, 82*4882a593Smuzhiyun rdimm2, 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #endif 87