1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2016 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <fsl_ddr_sdram.h>
9*4882a593Smuzhiyun #include <fsl_ddr_dimm_params.h>
10*4882a593Smuzhiyun #include "ddr.h"
11*4882a593Smuzhiyun #ifdef CONFIG_FSL_DEEP_SLEEP
12*4882a593Smuzhiyun #include <fsl_sleep.h>
13*4882a593Smuzhiyun #endif
14*4882a593Smuzhiyun #include <asm/arch/clock.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
17*4882a593Smuzhiyun
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)18*4882a593Smuzhiyun void fsl_ddr_board_options(memctl_options_t *popts,
19*4882a593Smuzhiyun dimm_params_t *pdimm,
20*4882a593Smuzhiyun unsigned int ctrl_num)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
23*4882a593Smuzhiyun ulong ddr_freq;
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun if (ctrl_num > 1) {
26*4882a593Smuzhiyun printf("Not supported controller number %d\n", ctrl_num);
27*4882a593Smuzhiyun return;
28*4882a593Smuzhiyun }
29*4882a593Smuzhiyun if (!pdimm->n_ranks)
30*4882a593Smuzhiyun return;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun pbsp = udimms[0];
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
35*4882a593Smuzhiyun * freqency and n_banks specified in board_specific_parameters table.
36*4882a593Smuzhiyun */
37*4882a593Smuzhiyun ddr_freq = get_ddr_freq(0) / 1000000;
38*4882a593Smuzhiyun while (pbsp->datarate_mhz_high) {
39*4882a593Smuzhiyun if (pbsp->n_ranks == pdimm->n_ranks) {
40*4882a593Smuzhiyun if (ddr_freq <= pbsp->datarate_mhz_high) {
41*4882a593Smuzhiyun popts->clk_adjust = pbsp->clk_adjust;
42*4882a593Smuzhiyun popts->wrlvl_start = pbsp->wrlvl_start;
43*4882a593Smuzhiyun popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
44*4882a593Smuzhiyun popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
45*4882a593Smuzhiyun goto found;
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun pbsp_highest = pbsp;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun pbsp++;
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun if (pbsp_highest) {
53*4882a593Smuzhiyun printf("Error: board specific timing not found for %lu MT/s\n",
54*4882a593Smuzhiyun ddr_freq);
55*4882a593Smuzhiyun printf("Trying to use the highest speed (%u) parameters\n",
56*4882a593Smuzhiyun pbsp_highest->datarate_mhz_high);
57*4882a593Smuzhiyun popts->clk_adjust = pbsp_highest->clk_adjust;
58*4882a593Smuzhiyun popts->wrlvl_start = pbsp_highest->wrlvl_start;
59*4882a593Smuzhiyun popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
60*4882a593Smuzhiyun popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
61*4882a593Smuzhiyun } else {
62*4882a593Smuzhiyun panic("DIMM is not supported by this board");
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun found:
65*4882a593Smuzhiyun debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
66*4882a593Smuzhiyun pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun popts->data_bus_width = 0; /* 64-bit data bus */
69*4882a593Smuzhiyun popts->otf_burst_chop_en = 0;
70*4882a593Smuzhiyun popts->burst_length = DDR_BL8;
71*4882a593Smuzhiyun popts->bstopre = 0; /* enable auto precharge */
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /*
74*4882a593Smuzhiyun * Factors to consider for half-strength driver enable:
75*4882a593Smuzhiyun * - number of DIMMs installed
76*4882a593Smuzhiyun */
77*4882a593Smuzhiyun popts->half_strength_driver_enable = 0;
78*4882a593Smuzhiyun /*
79*4882a593Smuzhiyun * Write leveling override
80*4882a593Smuzhiyun */
81*4882a593Smuzhiyun popts->wrlvl_override = 1;
82*4882a593Smuzhiyun popts->wrlvl_sample = 0xf;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /*
85*4882a593Smuzhiyun * Rtt and Rtt_WR override
86*4882a593Smuzhiyun */
87*4882a593Smuzhiyun popts->rtt_override = 0;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /* Enable ZQ calibration */
90*4882a593Smuzhiyun popts->zq_en = 1;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
93*4882a593Smuzhiyun popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
94*4882a593Smuzhiyun DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun /* optimize cpo for erratum A-009942 */
97*4882a593Smuzhiyun popts->cpo_sample = 0x70;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
fsl_initdram(void)100*4882a593Smuzhiyun int fsl_initdram(void)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun phys_size_t dram_size;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
105*4882a593Smuzhiyun gd->ram_size = fsl_ddr_sdram_size();
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun return 0;
108*4882a593Smuzhiyun #else
109*4882a593Smuzhiyun puts("Initializing DDR....using SPD\n");
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun dram_size = fsl_ddr_sdram();
112*4882a593Smuzhiyun #endif
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun erratum_a008850_post();
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun gd->ram_size = dram_size;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun return 0;
119*4882a593Smuzhiyun }
120