1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2014 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * FSL DCU Framebuffer driver
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <asm/io.h>
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <fsl_dcu_fb.h>
12*4882a593Smuzhiyun #include <i2c.h>
13*4882a593Smuzhiyun #include "div64.h"
14*4882a593Smuzhiyun #include "../common/diu_ch7301.h"
15*4882a593Smuzhiyun #include "ls1021aqds_qixis.h"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
18*4882a593Smuzhiyun
select_i2c_ch_pca9547(u8 ch)19*4882a593Smuzhiyun static int select_i2c_ch_pca9547(u8 ch)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun int ret;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
24*4882a593Smuzhiyun if (ret) {
25*4882a593Smuzhiyun puts("PCA: failed to select proper channel\n");
26*4882a593Smuzhiyun return ret;
27*4882a593Smuzhiyun }
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun return 0;
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun
dcu_set_pixel_clock(unsigned int pixclock)32*4882a593Smuzhiyun unsigned int dcu_set_pixel_clock(unsigned int pixclock)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun unsigned long long div;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun div = (unsigned long long)(gd->bus_clk / 1000);
37*4882a593Smuzhiyun div *= (unsigned long long)pixclock;
38*4882a593Smuzhiyun do_div(div, 1000000000);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun return div;
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
platform_dcu_init(unsigned int xres,unsigned int yres,const char * port,struct fb_videomode * dcu_fb_videomode)43*4882a593Smuzhiyun int platform_dcu_init(unsigned int xres, unsigned int yres,
44*4882a593Smuzhiyun const char *port,
45*4882a593Smuzhiyun struct fb_videomode *dcu_fb_videomode)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun const char *name;
48*4882a593Smuzhiyun unsigned int pixel_format;
49*4882a593Smuzhiyun int ret;
50*4882a593Smuzhiyun u8 ch;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /* Mux I2C3+I2C4 as HSYNC+VSYNC */
53*4882a593Smuzhiyun ret = i2c_read(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
54*4882a593Smuzhiyun 1, &ch, 1);
55*4882a593Smuzhiyun if (ret) {
56*4882a593Smuzhiyun printf("Error: failed to read I2C @%02x\n",
57*4882a593Smuzhiyun CONFIG_SYS_I2C_QIXIS_ADDR);
58*4882a593Smuzhiyun return ret;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun ch &= 0x1F;
61*4882a593Smuzhiyun ch |= 0xA0;
62*4882a593Smuzhiyun ret = i2c_write(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
63*4882a593Smuzhiyun 1, &ch, 1);
64*4882a593Smuzhiyun if (ret) {
65*4882a593Smuzhiyun printf("Error: failed to write I2C @%02x\n",
66*4882a593Smuzhiyun CONFIG_SYS_I2C_QIXIS_ADDR);
67*4882a593Smuzhiyun return ret;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun if (strncmp(port, "hdmi", 4) == 0) {
71*4882a593Smuzhiyun unsigned long pixval;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun name = "HDMI";
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun pixval = 1000000000 / dcu_fb_videomode->pixclock;
76*4882a593Smuzhiyun pixval *= 1000;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM);
79*4882a593Smuzhiyun select_i2c_ch_pca9547(I2C_MUX_CH_CH7301);
80*4882a593Smuzhiyun diu_set_dvi_encoder(pixval);
81*4882a593Smuzhiyun select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
82*4882a593Smuzhiyun } else {
83*4882a593Smuzhiyun return 0;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun pixel_format = 32;
89*4882a593Smuzhiyun fsl_dcu_init(xres, yres, pixel_format);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun return 0;
92*4882a593Smuzhiyun }
93